K4H1G0638B

www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) DDR SDRAM Stacked 1Gb B-die DDR SDRAM Specification (x4/x8) Revision 1.1 Rev. 1.1 August. 2003 www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) st. 1Gb B-die Revision History Revision 0.0 (May, 2003) - First version for internal review. Revision 1.0 (June, 2003) - Deleted "B3" speed. Revision 1.1 (August, 2003) - Corrected typo. DDR SDRAM Rev. 1.1 August. 2003 www.DataSheet4U.com DDR SDRAM stacked 1Gb B-die (x4/x8) Key Features Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe DQS Four banks operation Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs -. Read latency 2, 2.5 (clock) -. Burst length (2, 4, 8) -. Burst type (sequential & interleave) All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input DM for write masking only (x4, x8) Auto & Self refresh 7.8us refresh interval(8K/64ms refresh) Maximum burst refresh cycle : 8 66pin TSOP II package DDR SDRAM Ordering Information Part No. K4H1G0638B-TC/LAA K4H1G0638B-TC/LA2 K4H1G0638B-TC/LB0 K4H1G0738B-TC/LAA K4H1G0738B-TC/LA2 K4H1G0738B-TC/LB0 st.128M x 8 st.256M x 4 Org. Max Freq. AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2.5) AA(DDR266@CL=2) A2(DDR266@CL=2) B0(DDR266@CL=2...