DatasheetsPDF.com

K7B163635B Dataheets PDF



Part Number K7B163635B
Manufacturers Samsung Electronics
Logo Samsung Electronics
Description 512Kx36 & 1Mx18 Synchronous SRAM
Datasheet K7B163635B DatasheetK7B163635B Datasheet (PDF)

K7B163635B K7B161835B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVID.

  K7B163635B   K7B163635B


Document
K7B163635B K7B161835B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 18Mb B-die Sync. SRAM Specification 100TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. -1- July 2005 Rev 1.0 K7B163635B K7B161835B Document Title www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Update the DC current spec(ICC, ISB) 1. Change the ISB,ISB1,ISB2 - ISB ; from 120mA to 170mA - ISB1 ; from 80mA to 150mA - ISB2 ; from 80mA to 130mA 1. Remove the 1.8V Vdd voltage level 1. Remove the -85 speed bin 1. Finalize the datasheet Draft Date Mar. 23. 2004 May. 21, 2004 Sep. 21. 2004 Remark Advance Preliminary Preliminary 0.3 0.4 1.0 Oct. 18, 2004 Jan. 04, 2005 July 18, 2005 Preliminary Preliminary Final -2- July 2005 Rev 1.0 K7B163635B K7B161835B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 16Mb SB/SPB Synchronous SRAM Ordering Information Org. Part Number Mode VDD Speed SB ; Access Time(ns) SPB ; Cycle Time(MHz) 7.5ns 250/167MHz 200MHz 7.5ns 250/167MHz 200MHz P : Lead free 100TQFP I ; Industrial Temp.Range PKG Temp K7B161835B-Q(P)C(I)75 1Mx18 K7A161830B-Q(P)C(I)25/16 K7A161831B-Q(P)C(I)20 K7B163635B-Q(P)C(I)75 512Kx36 K7A163630B-Q(P)C(I)25/16 K7A163631B-Q(P)C(I)20 SB SPB(2E1D) SPB(2E2D) SB SPB(2E1D) SPB(2E2D) 3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5 3.3/2.5 C ; Commercial Q : 100TQFP Temp.Range -3- July 2005 Rev 1.0 K7B163635B K7B161835B www.DataSheet4U.com 512Kx36 & 1Mx18 Synchronous SRAM 512Kx36 & 1Mx18-Bit Synchronous Burst SRAM FEATURES • Synchronous Operation. • On-Chip Address Counter. • Self-Timed Write Cycle. • On-Chip Address and Control Registers. • VDD= 2.5 or 3.3V +/- 5% Power Supply. • 5V Tolerant Inputs Except I/O Pins. • Byte Writable Function. • Global Write Enable Controls a full bus-width write. • Power Down State via ZZ Signal. • LBO Pin allows a choice of either a interleaved burst or a linear burst. • Three Chip Enables for simple depth expansion with No Data Contention only for TQFP. • Asynchronous Output Enable Control. • ADSP, ADSC, ADV Burst Control Pins. • TTL-Level Three-State Output. • 100-TQFP-1420A (Lead and Lead free package) • Operating in commeical and industrial temperature range. GENERAL DESCRIPTION The K7B163635B and K7B161835B are 18,874,368-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 512K(1M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of WEx and BW when GW is high. And with CS1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the address status processor(ADSP) or address status cache controller(ADSC) inputs. Subsequent burst addresses are generated internally in the system′s burst sequence and are controlled by the burst address advance(ADV) input. LBO pin is DC operated and determines burst sequence(linear or interleaved). ZZ pin controls Power Down State and reduces Stand-by current regardless of CLK. The K7B163635B and K7B161835B are fabricated using SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple power and ground pins are utilized to minimize ground bounce. FAST ACCESS TIMES PARAMETER Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE -75 8.5 7.5 3.5 Unit ns ns ns LOGIC BLOCK DIAGRAM CLK LBO CONTROL REGISTER ADV ADSC BURST CONTROL LOGIC BURST ADDRESS COUNTER A0~A1 A0~A18 or A0~A19 ADDRESS REGISTER A2~A18 or A2~A19 A′0~A′1 512Kx36, 1Mx18 MEMORY ARRAY ADSP CS1 CS2 CS2 GW BW WEx (x=a,b,c,d or a,b) OE ZZ DATA-IN REGISTER CONTROL REGISTER CONTROL LOGIC OUTPUT BUFFER DQa0 ~ DQd7 or DQa0 ~ DQb7 DQPa ~ DQPd DQPa,DQPb -4- July 2005 Rev 1.0 K7B16363.


K7B161835B K7B163635B TZA1049


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)