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74AUP1G34 Dataheets PDF



Part Number 74AUP1G34
Manufacturers NXP
Logo NXP
Description Low-power buffer
Datasheet 74AUP1G34 Datasheet74AUP1G34 Datasheet (PDF)

74AUP1G34 Low-power buffer Rev. 01 — 4 August 2005 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range f.

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74AUP1G34 Low-power buffer Rev. 01 — 4 August 2005 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP1G34 provides the single buffer. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-C exceeds 2000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C Philips Semiconductors 74AUP1G34 Low-power buffer www.DataSheet4U.com 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3 ns. Symbol Parameter Conditions CL = 5 pF; RL = 1 MΩ; VCC = 0.8 V CL = 5 pF; RL = 1 MΩ; VCC = 1.1 V to 1.3 V CL = 5 pF; RL = 1 MΩ; VCC = 1.4 V to 1.6 V CL = 5 pF; RL = 1 MΩ; VCC = 1.65 V to 1.95 V CL = 5 pF; RL = 1 MΩ; VCC = 2.3 V to 2.7 V CL = 5 pF; RL = 1 MΩ; VCC = 3.0 V to 3.6 V Ci CPD input capacitance power dissipation capacitance VCC = 1.8 V; f = 10 MHz VCC = 3.3 V; f = 10 MHz [1] [2] [1] [2] Min 2.6 2.1 1.8 1.5 1.4 - Typ 15.0 4.7 3.4 2.9 2.3 2.1 0.8 3.5 4.3 Max 9.2 5.7 4.5 3.5 3.2 - Unit ns ns ns ns ns ns pF pF pF tPHL, tPLH propagation delay A to Y [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. The condition is VI = GND to VCC. [2] 4. Ordering information Table 2: Ordering information Package Temperature range Name 74AUP1G34GW 74AUP1G34GM −40 °C to +125 °C −40 °C to +125 °C TSSOP5 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm Version SOT353-1 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 5. Marking Table 3: Marking Marking code aN aN Type n.


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