IS41C85120A

IS41C85120A IS41LV85120A 512K x 8 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden JEDEC standard pinout Single power supply 5V ± 10% (IS41C85120A) 3.3V ± 10% (IS41LV85120A) Lead-free available ISSI APRIL 2005 ® www.DataSheet4U.com DESCRIPTION The ISSI IS41C85120A and IS41LV85120A are 524,288 x 8bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 8-bit word. The Byte Write control, of upper and lower byte, makes the IS41C85120A and IS41LV85120A ideal for use in 16 and 32-bit wide data bus systems. These features make the IS41C85120A and IS41LV85120A ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C85120A and IS41LV85120A are available in a 28-pin, 400-mil SOJ package. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -60 60 15 30 40 110 Unit ns ns ns ns ns PIN CONFIGURATION 28-Pin SOJ VCC I/O0 I/O1 I/O2 I/O3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I/O7 I/O6 ...