DS99R106

DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.DataSheet4U.com DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. ■ Internal DC Balancing encode/decode – Supports AC■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Features ■ 3 MHz–40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions ■ Capable to drive shielded twisted-pair cable ■ User selectable clock edge for parallel data on both Transmitter and Receiver coupling interface with no external coding required Individual power-down...