RC32365

IDT T M InterpriseT M Integrated Communications Processor www.DataSheet4U.com RC32365 Device Overview The RC32365 device is a member of the IDT™ Interprise™ family of integrated communications processors. This device is designed to address a range of communications applications that require the efficient processing of IPSec algorithms. These applications inclu de gateways, wireless access poin ts, and virtual private network (VPN) equipment. The key to the RC32365’s efficient processin g of IPSec algorithms is a highly progammable security engine which off-loads the CPU core of encryptio n/decryptio n, hashing, and paddin g tasks. Features List x RC32300 32-bit CPU core – 32-bit MIPS instruction set – Supports big or lit tle endian operation – MMU – 16-entry TLB – Supports varia ble page sizes and enhanced write algorithm – Supports variable number of locked entries – 8KB Instructio n Cache – 2-way set associa tive – LRU replacement algorithm – 4 word lin e size – Sub-block ordering – Word parity – Per line cache lockin g – 2KB Data Cache 2-way set associa tive LRU replacement algorithm 4 word lin e size Sub-block ordering Byte parity Per line cache lockin g Can be programmed on a page basis to implement writethrough no write allocate, write-through write allocate, or write-back algorit hms – Enhanced EJTAG and JTAG Interfaces – Compatible with IEEE Std. 1149.1-1990 x Security Engine – Dedicated DMA channels for high speed data transfers to and from the security engine ...