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BUK9MNN-65PKK
Dual TrenchPLUS FET Logic Level FET
Rev. 01 — 27 May 2010 Objective data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring very low on-state resistance, integrated current sensing transistors and over temperature protection diodes.
1.2 Features and benefits
Integrated current sensors Integrated temperature sensors
1.3 Applications
Lamp switching Motor drive systems Power distribution Solenoid drivers
1.4 Quick reference data
Table 1. Symbol RDSon Quick reference data Parameter drain-source on-state resistance ratio of drain current to sense current drain-source breakdown voltage Conditions VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure 16; see Figure 17 Tj = 25 °C; VGS = 5 V; see Figure 18 ID = 250 µA; VGS = 0 V; Tj = 25 °C Min Typ Max Unit mΩ
FET1 and FET2 static characteristics 30.6 36
ID/Isense
2242 2491 2740 A/A
V(BR)DSS
65
-
-
V
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BUK9MNN-65PKK
Dual TrenchPLUS FET Logic Level FET
2. Pinning information
Table 2. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pinning information Symbol Description G1 IS1 D1 A1 C1 G2 IS2 D2 A2 C2 D2 KS2 S2 S2 D2 D1 KS1 S1 S1 D1 gate 1 current sense 1 drain anode 1 cathode 1 gate 2 current sense 2 drain 2 anode 2 cathode 2 drain 2 Kelvin source 2 source 2 source 2 drain 2 drain 1 Kelvin source 1 source 1 source 1 drain 1
1 10 G1 IS1 S1 KS1 C1 G2 IS2 S2 KS2 C2
003aaa745
Simplified outline
20 11
Graphic symbol
D1 A1 D2 A2
FET1
FET2
SOT163-1 (SO20)
3. Ordering information
Table 3. Ordering information Package Name BUK9MNN-65PKK SO20 Description plastic small outline package; 20 leads; body width 7.5 mm Version SOT163-1 Type number
BUK9MNN-65PKK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 May 2010
2 of 18
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NXP Semiconductors
BUK9MNN-65PKK
Dual TrenchPLUS FET Logic Level FET
4. Limiting values
Table 4. Symbol FET1 and FET2 VDS VDGR VGS ID IDM Ptot Tstg Tj Visol(FET-TSD) drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature FET to temperature sense diode isolation voltage source current peak source current non-repetitive drain-source avalanche energy electrostatic discharge voltage Tsp = 25 °C single pulse; tp ≤ 10 µs; Tsp = 25 °C ID = 13.6 A; Vsup = 65 V; VGS = 5 V; Tj(init) = 25 °C; unclamped; see Figure 3
[3][4][5] [2][1]
Limiting values Parameter Conditions 25 °C ≤ Tj ≤ 150 °C RGS = 20 kΩ; 25 °C ≤ Tj ≤ 150 °C VGS = 5 V; Tsp = 25 °C; see Figure 1 VGS = 5 V; Tsp = 100 °C; see Figure 1 Tsp = 25 °C; single pulse; tp ≤ 10 µs; see Figure 4 Tsp = 25 °C; see Figure 2
[1] [2][1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Min -15 -55 -55 Typ Max 65 65 15 7.1 4.5 96.6 3.57 150 150 100 Unit V V V A A A W °C °C V
FET1 and FET2 source-drain diode IS ISM EDS(AL)S 5 96.6 165 A A mJ
FET1 and FET2 avalanche ruggedness
FET1 and FET2 electrostatic discharge VESD HBM; C = 100 pF; R = 1.5 kΩ; all pins HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to pins 6, 7, 12, 13 and 14 shorted HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to pins 1, 2, 17, 18 and 19 shorted
[1] [2] [3] [4] [5] Current is limited by package. Single device conducting. Single-pulse avalanche rating limited by maximum junction temperature of 150 °C. Repetitive rating defined in avalanche rating figure. Refer to application note AN10273 for further information.
-
-
0.15 4
kV kV
-
-
4
kV
BUK9MNN-65PKK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 May 2010
3 of 18
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BUK9MNN-65PKK
Dual TrenchPLUS FET Logic Level FET
8 ID (A) 6
001aal886
120 Pder (%) 80
003aab388
4
40
2
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 200 Tsp (°C)
Fig 1.
Continuous drain current as a function of solder point temperature, FET1 and FET2
Fig 2.
Normalized total power dissipation as a function of solder point temperature, FET1 and FET2
001aal682 (1)
10 IAL (A) 1
(2)
(3)
10−1
10−2 10−3
10−2
10−1
1 tAL (ms)
10
Fig 3.
Single-Pulse and repetitive avalanche rating; avalanche current as a function of avalanche time
BUK9MNN-65PKK
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 — 27 May 2010
4 of 18
w w w . D a t a S h e e t 4 U . c o m
NXP Semiconductors
BUK9MNN-65PKK
Dual TrenchPLUS FET Logic Level FET
103 ID (A) 102 Limit RDSon = VDS / ID
001aal757
tp = 10 μs 10 100 μs
1 DC 10−1
1 ms 10 ms 100 ms
10−2 10−1
1
10 VDS (V)
102
Fig 4.
Safe .