Thumb-based Microcontrollers. AT91SAM9M10 Datasheet

AT91SAM9M10 Datasheet PDF, Equivalent


Part Number

AT91SAM9M10

Description

AT91 ARM Thumb-based Microcontrollers

Manufacture

ATMEL

Total Page 30 Pages
PDF Download
Download AT91SAM9M10 Datasheet PDF


AT91SAM9M10 Datasheet
www.DataSheet4U.com
Features
400 MHz ARM926EJ-S™ ARM® Thumb® Processor
– 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
Memories
– DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR
– External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static
Memories, CompactFlash®, SLC NAND Flash with ECC
– One 64-KByte internal SRAM, single-cycle access at system speed or processor
speed through TCM interface
– One 64-KByte internal ROM, embedding bootstrap routine
Peripherals
– Multi-format Video Decoder
– LCD Controller supporting STN and TFT displays up to 1280*860
– ITU-R BT. 601/656 Image Sensor Interface
– USB Device High Speed, USB Host High Speed and USB Host Full Speed with On-
Chip Transceiver
– 10/100 Mbps Ethernet MAC Controller
– Two High Speed Memory Card Hosts (SDIO, SDCard, MMC)
– AC'97 controller
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 16-bit Timer/Counters
– Two Synchronous Serial Controllers (I2S mode)
– Four-channel 16-bit PWM Controller
– Two Two-wire Interfaces
– Four USARTs with ISO7816, IrDA, Manchester and SPI modes
– 8-channel 10-bit ADC with 4-wire Touch Screen support
System
– 133 MHz twelve 32-bit layer AHB Bus Matrix
– 37 DMA Channels
– Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash
– Reset Controller with on-chip Power-on Reset
– Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators
– Internal Low-power 32 kHz RC Oscillator
– One PLL for the system and one 480 MHz PLL optimized for USB High Speed
– Two Programmable External Clock Signals
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
I/O
– Five 32-bit Parallel Input/Output Controllers
– 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with
Schmitt trigger input
Package
– 324-ball TFBGA, pitch 0.8 mm
AT91 ARM
Thumb-based
Microcontrollers
AT91SAM9M10
Preliminary
6355A–ATARM–06-Jan-10

AT91SAM9M10 Datasheet
www.DataSheet4U.com
1. Description
The AT91SAM9M10 is a multimedia enabled mid-range ARM926-based embedded MPU run-
ning at 400MHz, combining user interfaces, video playback and connectivity. It includes
hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio, Ether-
net 10/100 and high speed USB and SDIO.
The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263. The SAM9M10
also provides hardware image post-processing, such as image scaling, color conversion and
image rotation.
The AT91SAM9M10 supports the latest generation of DDR2 and NAND Flash memory inter-
faces for program and data storage. An internal 133 MHz multi-layer bus architecture associated
with 37 DMA channels, a dual external bus interface and distributed memory including a 64-
KByte SRAM which can be configured as a tightly coupled memory (TCM) sustains the high
bandwidth required by the processor and the high speed peripherals.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory
interface and peripheral I/Os. This feature completely eliminates the need for any external level
shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.
The AT91SAM9M10 power management controller features efficient clock gating and a battery
backup section minimizing power consumption in active and standby modes.
The AT91SAM9M10 device is particularly well suited for media-rich displays and control panels
in home and commercial buildings, POS terminals, entertainment systems, internet appliances
and medical.
2 AT91SAM9M10
6355A–ATARM–06-Jan-10


Features Datasheet pdf www.DataSheet4U.com Features • 400 MH z ARM926EJ-S™ ARM® Thumb® Processor – 32 KBytes Data Cache, 32 KBytes In struction Cache, MMU • Memories – DDR2 Controller 4-bank DDR2/LPDDR, SDRA M/LPSDR – External Bus Interface supp orting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash®, SLC NA ND Flash with ECC – One 64-KByte inte rnal SRAM, single-cycle access at syste m speed or processor speed through TCM interface – One 64-KByte internal ROM , embedding bootstrap routine Periphera ls – Multi-format Video Decoder – L CD Controller supporting STN and TFT di splays up to 1280*860 – ITU-R BT. 601 /656 Image Sensor Interface – USB Dev ice High Speed, USB Host High Speed and USB Host Full Speed with OnChip Transc eiver – 10/100 Mbps Ethernet MAC Cont roller – Two High Speed Memory Card H osts (SDIO, SDCard, MMC) – AC'97 cont roller – Two Master/Slave Serial Peri pheral Interfaces – Two Three-channel 16-bit Timer/Counters – Two Synchronous Serial Controllers (I2S mode) – Four-channel 16-bit PWM Con.
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