M24L16161ZA

ESMT Revision History : Revision 1.0 (Jul. 4, 2007) - Original www.DataSheet4U.com M24L16161ZA Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007 Revision : 1.0 1/15 ESMT PSRAM Features ‧Wide voltage range: 2.2V–3.6V Access Time: 70 ns Ultra-low active power— Typical active current: 3 mA @ f = 1 MHz— Typical active current: 18 mA @ f = fmax Ultra low standby power Automatic power-down when deselected CMOS for optimum speed/power Deep Sleep Mode Offered in a Lead-Free 48-ball BGA package Operating Temperature: –40°C to +85°C www.DataSheet4U.com M24L16161ZA 16-Mbit (1M x 16) Pseudo Static RAM are disabled ( OE HIGH), both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). To write to the device, take Chip Enable ( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memo...