M24L216128SA

ESMT PSRAM Features Wide voltage range: 2.7V–3.6V Access Time: 55 ns, 70 ns Ultra-low active power — Typical active current: 1mA @ f = 1 MHz — Typical active current: 14 mA @ f = fmax (For 55-ns) —Typical active current: 8 mA @ f = fmax (For 70-ns) Ultra low standby power Automatic power-down when deselected CMOS for optimum speed/power www.DataSheet4U.com M24L216128SA 2-Mbit (128K x 16) Pseudo Static RAM when both Byte High Enable and Byte Low Enable are disabled ( BHE , BLE HIGH), or during a write operation ( CE LOW and WE LOW). Writing to the device is accomplished by asserting Chip Enable ( CE LOW) and Write Enable ( WE ) input LOW. If Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable ( BHE ) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by asserting Chip Enable ( CE LOW) and Output Enable ( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. Refer to the truth table for a complete description of read and write modes. Functional Description The M24L216128SA is a high-performance CMOS Pseudo Static RA...