M24L416256DA

ESMT PSRAM Features Advanced low-power architecture High speed: 55 ns, 60 ns and 70 ns Wide voltage range: 2.7V to 3.6V Typical active current: 1 mA @ f = 1 MHz Low standby power Automatic power-down when deselected www.DataSheet4U.com M24L416256DA 4-Mbit (256K x 16) Pseudo Static RAM reducing power consumption dramatically when deselected ( CE1 HIGH, CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CE1 HIGH, CE2 LOW, OE is HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). Reading from the device is accomplished by asserting the Chip Enables ( CE1 LOW and CE2 HIGH) and Output Enable( OE ) LOW while forcing the Write Enable ( WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data from the memory location specified by the address pins A0 through A17 will appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table for a complete description of read and write modes. Functional Description The M24L416256DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones. The device can be put into standby mode Elite Semiconductor Memory Technology Inc. Publication Dat...