Document
Freescale Semiconductor Data Sheet: Advance Information
An Energy Efficient Solution by Freescale
Document Number: MC9S08GW64 Rev. 1, 5/2010
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MC9S08GW64 Series
Covers: MC9S08GW64 and MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
MC9S08GW64
80-LQFP Case 917A 14 × 14
64-LQFP Case 840F 10 × 10
comparator can be used as hardware breakpoint. Full mode, Comparator A compares address and Comparator B compares data. Supports both tag and force breakpoints
Peripherals
– New version of S08 core with same performace as traditional S08 and lower power – Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 2.15 V to 1.8 V, across temperature range of –40 °C to 85 °C – HC08 instruction set with added BGND instruction – Support for up to 48 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents
Power-Saving Modes
– Two low power stop modes and reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 μs typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS – Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz; optional clock source for ICS – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference (XOSC1, XOSC2); precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz internal clock source or bus clock – Low-voltage warning with interrupt – Low-voltage detection with reset or interrupt – Illegal opcode and illegal address detection with reset – Flash block protection
Development Support
– LCD — up to 4×40 or 8×36 LCD driver with internal charge pump and option to provide an internally regulated LCD reference that can be trimmed for contrast control – ADC16 — two analog-to-digital converters; 16-bit resolution; one dedicated differential per ADC; up to 16-ch; up to 2.5 μs conversion time for 12-bit mode; automatic compare function; hardware averaging; calibration registers; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V – PRACMP —three rail to rail programmable reference analog comparator; up to 8 in.