AS81F641642C

www.DataSheet4U.com AS81F641642C ME MOR Y FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 15.6 µ s refresh interval 1M x 16 Bit x 4 Banks SYNCHRONOUS DYNAMIC RAM ORDERING INFORMATION 54 Pin TSOP (Type II) (400mil x 875mil ) PRODUCT NO. AS81F641642C-6 AS81F641642C-7 MAX FREQ. 166MHz 143MHz PACKAGE TSOP II AS81F641642C-6P AS81F641642C-7P 166MHz 143MHz TSOP II PB FREE GENERAL DESCRIPTION The AS81F641642C is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. PIN ASSIGNMENT Top View V DD DQ 0 VDD Q DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VDD Q DQ 5 DQ 6 VSSQ DQ 7 V DD L DQ M WE C AS R AS CS A 13 A 12 A 10 /AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 VSSQ DQ14 DQ13 VDD Q DQ12 DQ11 VSSQ ...