H5DU1262GTR

www.DataSheet4U.com 128Mb DDR SDRAM H5DU1262GTR This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / May 2009 1 www.DataSheet4U.com H5DU1262GTR Series Revision History Revision No. 0.1 1.0 First version Release History Draft Date Feb. 2009 May 2009 Remark PPre Rev. 1.0 / May 2009 2 www.DataSheet4U.com H5DU1262GTR Series PPre DESCRIPTION The H5DU1262GTR is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2. FEATURES VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333 ,400 and 500) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data ...