DS92LV0411

www.DataSheet4U.com DS92LV0411 / DS92LV0412 5- 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface PRELIMINARY DS92LV0411 / DS92LV0412 May 26, 2010 5 - 50 MHz Channel Link II Serializer/Deserializer with LVDS Parallel Interface General Description The DS92LV0411 (serializer) and DS92LV0412 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV0411/DS92LV0412 enables applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to incoming data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation. The DS92LV0411 and DS92LV0412 are programmable though an I2C interface as well as by pins. A built-in ATSPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0411 and DS92LV0412 can be used interchangeably with the DS92LV2411 or DS92LV2412. This allows designers the ...