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S3C2400 Dataheets PDF



Part Number S3C2400
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description RISC MICROPROCESSOR
Datasheet S3C2400 DatasheetS3C2400 Datasheet (PDF)

www.DataSheet4U.com S3C2400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1 PRODUCT OVERVIEW INTRODUCTION SAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (STN & TFT), 2-chan.

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www.DataSheet4U.com S3C2400 RISC MICROPROCESSOR PRODUCT OVERVIEW 1 PRODUCT OVERVIEW INTRODUCTION SAMSUNG's S3C2400 16/32-bit RISC microprocessor is designed to provide a cost-effective, low power, small die size and high performance micro-controller solution for hand-held devices and general applications. To reduce total system cost, S3C2400 also provides the following: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (STN & TFT), 2-channel UART with handshake, 4-channel DMA, System Manager (chip select logic, EDO/SDRAM controller), 4-channel Timers with PWM, I/O Ports, RTC, 8channel 10-bit ADC, IIC-BUS interface, IIS-BUS interface, USB Host, USB Device, Multi-Media Card Interface, SPI and PLL for clock generation. The S3C2400 was developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost-sensitive and power sensitive applications. Also S3C2400 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture) An outstanding feature of the S3C2400 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with a 8-word line length. By providing complete set of common system peripherals, the S3C2400 minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include: • • • • • • • • • • • • • • • 1.8V internal, 3.3V external (I/O boundary) microprocessor with 16KB I-Cache, 16KB D-Cache, and MMU. External memory controller. (EDO/SDRAM Control, Chip Select logic) LCD controller (up to 4K color STN and 64K color TFT) with 1-ch LCD-dedicated DMA. 4-ch DMAs with external request pins 2-ch UART with handshake (IrDA1.0, 16-byte FIFO)/1-ch SPI 1-ch multi-master IIC-BUS/1-ch IIS-BUS controller MMC interface (ver 2.11) 2-port USB Host /1- port USB Device (ver 1.1) 4-ch PWM timers & 1-ch internal timer Watch Dog Timer 90-bit general purpose I/O ports/8-ch external interrupt source Power control: Normal, Slow, Idle, Stop and SL_IDLE mode 8-ch 10-bit ADC. RTC with calendar function. On-chip clock generator with PLL 1-1 www.DataSheet4U.com PRODUCT OVERVIEW S3C2400 RISC MICROPROCESSOR FEATURES Architecture • • • • Integrated system for hand-held devices and general embedded applications. 16/32-Bit RISC architecture and powerful instruction set with ARM920T CPU core. Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ARM920T CPU core supports the ARM debug architecture and has a Tracking ICE mode. Internal AMBA(Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB) Cache Memory • • • • • 64 way set-associative cache with I-Cache(16KB) and D-Cache(16KB). 8-words per line with one valid bit and two dirty bits per line Pseudo random or round robin replacement algorithm. Write through or write back cache operation to update the main memory. The write buffer can hold 16 words of data and four address. • • Clock & Power Manager • • Low power The on-chip MPLL and UPLL UPLL makes the clock for operating USB Host/Device. MPLL makes the clock for operating MCU at maximum 150Mhz @ 1.8V. Clock can be fed selectively to each function block by software. Power mode: Normal, Slow, Idle, Stop mode and SL_IDLE mode. Normal mode: Normal operating mode. Slow mode: Low frequency clock without PLL. Idle mode: Stop the clock for only CPU. Stop mode: All clocks are stopped. SL_IDLE mode: All clocks except LCD are stopped. Wake up by EINT[7:0] or RTC alarm interrupt from Stop mode. System Manager • • • • • • Little/Big Endian support. Address space: 32M bytes for each bank (Total 256Mbyte) Supports programmable 8/16/32-bit data bus width for each bank. Fixed bank start address and programmable bank size for 7 banks. Programmable bank start address and bank size for one bank. 8 memory banks. — 6 memory banks for ROM, SRAM etc. — 2 memory banks for ROM/SRAM/DRAM(EDO or Synchronous DRAM) Fully Programmable access cycles for all memory banks. Supports external wait signal to expend the bus cycle. Supports self-refresh mode in DRAM/SDRAM for power-down. Supports asymmetric/symmetric address of DRAM. • • • • • • • Interrupt Controller • 32 Interrupt sources (Watch dog timer, 5Timer, 6UART, 8External interrupts, 4 DMA, 2 RTC, 1 ADC, 1 IIC, 1 SPI, 1 MMC, 2 USB) Level/Edge mode on external interrupt source. Programmable polarity of edge and level. Supports FIQ (Fast Interrupt request) for very urgent interrupt request. • • • 1-2 www.DataSheet4U.com S3C2400 RISC MICROPROCESSOR PRODUCT OVERVIEW Timer with PWM (Pulse Width Modulation) • 4-.


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