Flash Memory. AT49LV8011T Datasheet

AT49LV8011T Datasheet PDF, Equivalent


Part Number

AT49LV8011T

Description

8-megabit (512K x 16/1M x 8) 3-volt Only Flash Memory

Manufacture

ATMEL

Total Page 18 Pages
PDF Download
Download AT49LV8011T Datasheet PDF


AT49LV8011T Datasheet
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Features
Single Supply for Read and Write: 2.7V to 3.3V (BV), 3.0V to 3.3V (LV)
Access Time – 90 ns
Sector Erase Architecture
Fourteen 32K Word (64K Byte) Sectors with Individual Write Lockout
Two 16K Word (32K Byte) Sectors with Individual Write Lockout
Two 8K Word (16K Byte) Sectors with Individual Write Lockout
Four 4K Word (8K Byte) Sectors with Individual Write Lockout
Fast Word Program Time – 20 µs
Fast Sector Erase Time 200 ms
Dual Plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors
Memory Plane B: Fourteen 32K Word Sectors
Erase Suspend Capability
Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
25 mA Active
10 µA Standby
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
Optional VPP Pin for Fast Programming
RESET Input for Device Initialization
Sector Program Unlock Command
TSOP and CBGA Package Options
Top or Bottom Boot Block Configuration Available
Description
The AT49BV/LV8011(T) is a 2.7- to 3.3-volt 8-megabit Flash memory organized as
524,288 words of 16 bits each or 1,048,576 bytes of 8 bits each. The x16 data
appears on I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided
into 22 sectors for erase operations. The device is offered in 48-pin TSOP and 48-ball
CBGA packages. The device has CE, and OE control signals to avoid any bus
Pin Configurations
(continued)
Pin Name
A0 - A18
CE
OE
WE
RESET
RDY/BUSY
VPP
I/O0 - I/O14
I/O15 (A-1)
BYTE
NC
VCCQ
Function
Addresses
Chip Enable
Output Enable
Write Enable
Reset
READY/BUSY Output
Optional Power Supply for Faster
Program/Erase Operations
Data Inputs/Outputs
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
Selects Byte or Word Mode
No Connect
Output Power Supply
8-megabit
(512K x 16/1M x 8)
3-volt Only
Flash Memory
AT49BV8011
AT49BV8011T
AT49LV8011
AT49LV8011T
Rev. 1265E01/00
1

AT49LV8011T Datasheet
www.DataSheet4U.com
TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
VPP
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 A16
47 BYTE
46 GND
45 I/O15/A-1
44 I/O7
43 I/O14
42 I/O6
41 I/O13
40 I/O5
39 I/O12
38 I/O4
37 VCC
36 I/O11
35 I/O3
34 I/O10
33 I/O2
32 I/O9
31 I/O1
30 I/O8
29 I/O0
28 OE
27 GND
26 CE
25 A0
CBGA Top View
12345
6
A
A3 A7 RDY/BUSY WE A9 A13
B
A4 A17 NC RESET A8 A12
C
A2 A6 A18 VPP A10 A14
D
A1 A5 NC NC A11 A15
E
A0 I/O0 I/O2 I/O5 I/O7 A16
F
CE I/O8 I/O10 I/O12 I/O14 BYTE
G
OE I/O9 I/O11 VCC I/O13 I/O15
/A-1
H
VSS I/O1 I/O3 I/O4 I/O6 VSS
contention. This device can be read or reprogrammed
using a single 2.7V power supply, making it ideally suited
for in-system programming.
The device powers on in the read mode. Command
sequences are used to place the device in other operation
modes such as Program and Erase. The device has the
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and VCC.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the Erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an Erase
cycle is detected by the Ready/Busy pin, Data polling, or by
the toggle bit.
A VPP pin is provided to improve program/erase times.
This pin can be tied to VCC. To take advantage of faster
programming and erasing, the pin should supply 4.5 to
5.5 volts during program and erase operations.
A 6-byte command (bypass unlock) sequence to remove
the requirement of entering the 3-byte program sequence
is offered to further improve programming time. After enter-
ing the 6-byte code, only single pulses on the write control
lines are required for writing into the device. This mode
(single-pulse byte/word program) is exited by powering
down the device, or by pulsing the RESET pin low for a
minimum of 50 ns and then bringing it back to VCC. Erase
and Erase Suspend/Resume commands will not work while
in this mode; if entered they will result in data being pro-
grammed into the device. It is not recommended that the
6-byte code reside in the software of the final product but
only exist in external programming code.
The BYTE pin controls whether the device data I/O pins
operate in the byte or word configuration. If the BYTE pin is
set at logic 1, the device is in word configuration,
I/O0 - I/O15 are active and controlled by CE and OE.
If the BYTE pin is set at logic 0, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated, and the I/O15 pin is used as an input for the
LSB (A-1) address function.
2 AT49BV/LV8011(T)


Features Datasheet pdf www.DataSheet4U.com Features • Single Supply for Read and Write: 2.7V to 3.3 V (BV), 3.0V to 3.3V (LV) • Access Ti me – 90 ns • Sector Erase Architect ure Fourteen 32K Word (64K Byte) Sector s with Individual Write Lockout Two 16K Word (32K Byte) Sectors with Individua l Write Lockout Two 8K Word (16K Byte) Sectors with Individual Write Lockout F our 4K Word (8K Byte) Sectors with Indi vidual Write Lockout Fast Word Program Time – 20 µs Fast Sector Erase Time – 200 ms Dual Plane Organization, Per mitting Concurrent Read while Program/E rase Memory Plane A: Four 4K Word, Two 8K Word and Two 16K Word Sectors Memory Plane B: Fourteen 32K Word Sectors Era se Suspend Capability – Supports Read ing/Programming Data from Any Sector by Suspending Erase of Any Different Sect or Low-power Operation – 25 mA Active – 10 µA Standby Data Polling, Toggl e Bit, Ready/Busy for End of Program De tection Optional VPP Pin for Fast Progr amming RESET Input for Device Initialization Sector Program Unlock Command TSOP and.
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