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Freescale Semiconductor Technical Data
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MMA68xx Rev 2, 06/2010
Dual Axis SPI Inertial Sensor
MMA68xx is a SPI-based, 2-axis, medium-g, over-damped lateral accelerometer designed for use in automotive airbag systems. Features • • • • • • • • ±20g to ±120 g full-scale range, independently specified for each axis 3.3 V or 5 V single supply operation SPI-compatible serial interface 10-bit digital signed or unsigned SPI data output Independent programmable arming functions for each axis Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz Optional offset cancellation with > 6s averaging period and < 0.25 LSB/s slew rate Pb-Free 16-Pin QFN-6x6 Package DUAL AXIS SPI INERTIAL SENSOR
MMA68xx
Bottom View
Referenced Documents • AEC-Q100, Revision G, dated May 14, 2007
16-PIN QFN CASE 1477-02
Top View
VSSA VSSA 12 CS 11 MOSI 10 SCLK 9 VCC 5 ARM_Y/PCM_Y 6 ARM_X/PCM_X 7 TEST/VPP 8 MISO N/C N/C
ORDERING INFORMATION
Device MMA6811QR2 MMA6813QR2 MMA6821QR2 MMA6823QR2 MMA6826QR2 MMA6827QR2 X-Axis Range ±60g ±50g ±120g ±120g ±60g ±120g Y-Axis Range ±25g ±50g ±25g ±60g ±60g ±120g Shipping Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel Tape & Reel VREGA 1 VSS 2 VREG 3 VSS 4
16 15 14 13 17
PIN CONNECTIONS
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VCC
VCC VREG VREGA
CS SCLK MOSI MISO
CS_A SCLK1 MOSI1 MISO1
CS_D SCLK2 MOSI2 MISO2
CS SCLK MOSI MISO
C1
C2
C3
MMA68xx
VSSA VSS
VPP/TEST ARM_X ARM_Y
Main MCU
Deployment IC
DEPLOY_EN1 DEPLOY_EN2
Figure 1. Application Diagram Table 1. External Component Recommendations
Ref Des C1 C2 C3 Type Ceramic Ceramic Ceramic Description 0.1 μF, 10%, 10 V Minimum, X7R 1 μF, 10%, 10 V Minimum, X7R 1 μF, 10%, 10 V Minimum, X7R Purpose VCC Power Supply Decoupling Voltage Regulator Output Capacitor (CREG) Voltage Regulator Output Capacitor (CREGA)
Device Orientation
xxxxxxx xxxxxxx
X: 0g Y: -1g
MMA68xx 2 Sensors Freescale Semiconductor
xxxxxxx xxxxxxx X: +1g Y: 0g
Figure 2. Device Orientation Diagram
xxxxxxx xxxxxxx X: 0g Y: +1g
xxxxxxx xxxxxxx X: -1g Y: 0g X: 0g Y: 0g X: 0g Y: 0g
EARTH GROUND
Internal Block Diagram
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VPP VCC VREG VSS VREGA
IIR Offset Compensation Linear Interpolation Cancellation Output Scaling Offset Monitor Clock CRC Generation Y-Axis Register Array SPI Mismatch Verification Y-Axis SPI ARM_Y
VSSA ARM_Y
Over-Damped Y-Axis g-Cell
SINC Filter
Low-Pass Filter
ΣΔ Converter
Clock & bias Generator 1 MHz Self Test Analog Regulator 8 MHz Digital
VREG
VREGA VCC SPI OTP Array I/O
CS SCLK MOSI MISO
1 MHz
Oscillator
Regulator
Voltage Monitoring
Memory
VREGA
Clock & bias Generator
VREG
ΣΔ Converter Over-Damped X-Axis g-Cell
Clock CRC Generation IIR SINC Filter Low-Pass Filter Compensation Linear Interpolation Offset Cancellation Clock Monitoring Offset Monitor X-Axis Register Array X-Axis SPI
Output Scaling ARM_X
ARM_X
Figure 3. Block Diagram
MMA68xx Sensors Freescale Semiconductor 3
1
PIN CONNECTIONS
VSSA 16 15 14 13 VREGA 1 VSS 2 VREG 3 VSS 4 5 ARM_Y/PCM_Y 6 ARM_X/PCM_X 7 TEST/VPP 8 MISO 17 12 CS 11 MOSI 10 SCLK 9 VCC VSSA N/C N/C
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Figure 4. 16-Pin QFN Package, Top View Table 2. Pin Description
Pin 1 2 3 4 5 Pin Name VREGA VSS VREG VSS ARM_Y/ PCM_Y Formal Name Analog Supply Digital GND Digital Supply Digital GND Definition This pin is connected to the power supply for the internal analog circuitry. An external capacitor must be connected between this pin and VSSA. Reference Figure 1. This pin is the power supply return node for the digital circuitry. This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between this pin and VSS. Reference Figure 1. This pin is the power supply return node for the digital circuitry.
Y-Axis The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the Arm Output / arming output is selected, ARM_Y can be configured as an open drain, active low output with a pull-up current; PCM Output or an open drain, active high output with a pull-down current. Alternatively, this pin can be configured as a digital output with PCM signal proportional to the Y axis acceleration data. Reference Section 3.8.9 and Section 3.8.9.1. If unused, this pin must be left unconnected. X-Axis The function of this pin is configurable via the DEVCFG register as described in Section 3.1.6.5. When the Arm Output / arming output is selected, ARM_X can be configured as an open drain, active low output with a pull-up current; PCM Output or an open drain, active high output with a pull-down current. Alternatively, this pin can be configured as a digital output with a PCM signal proportional to the X-axis acceleration data. Reference Section 3.8.9 and Section 3.8.9.1. If unused, this pin must be left unconnected. Programming This pin provides the power for factory programming of the OTP registers. This pin must be connec.