LP62S1024B-T

LP62S1024B-T Series Preliminary Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0.1 128K X 8 BIT LOW VOLTAGE CMOS SRAM History Initial issue Add 32L Pb-Free TSSOP package type Issue Date February 19, 2002 October 2, 2002 Remark Preliminary PRELIMINARY (October, 2002, Version 0.1) AMIC Technology, Corp. LP62S1024B-T Series Preliminary Features n Power supply range: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 30mA(max.) Standby: 5uA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm) forward type and 36-pin CSP packages 128K X 8 BIT LOW VOLTAGE CMOS SRAM General Description The LP62S1024B-T is a low operating current 1,048,576bit static random access memory organized as 131,072 words by 8 bits and operates on a low power voltage: 2.7V to 3.6V. It is built using AMIC's high performance CMOS process. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family O...