Document
NB4N111K
Clock Fanout Buffer, 1:10 Differential, 3.3 V, with HCSL Level Output
Description The NB4N111K is a differential input clock 1 to 10 HCSL fanout
buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential VLPECL, CML, or VLDS levels.Single
−ended LVPECL, CML, VLCMOS or VLTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 W on die termination resistors. Outputs can interface with LVDS with proper termination (See Figure 15).
The NB4N111K specifically guarantees low output–to–output skews. Optimal design, layout, and processing minimize skew within a device and from device to device. System designers can take advantage of the NB4N111K’s performance to distribute low skew clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and
400 MHz
• 340 ps Typical Rise and Fall Times • 800 ps Typical Propagation Delay • Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• <1 ps RMS Additive Clock jitter • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V • Differential HCSL Output Level or LVDS with Proper Termination • These are Pb−Free Devices
http://onsemi.com
1 32
QFN32 MN SUFFIX CASE 488AM
MARKING DIAGRAM*
32 1
NB4N 111K AWLYYWWG
A
= Assembly Site
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to Application Note AND8002/D.
VTCLK
CLK CLK
VTCLK VCC GND
Q0 Q0 Q1 Q1
Q8
Q8 Q9
RREF
IREF Q9
Figure 1. Pin Configuration (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
September, 2011 − Rev. 5
Publication Order Number: NB4N111K/D
IREF 1 VTCLK 2
CLK 3 CLK 4 VTCLK 5
Q9 6 Q9 7 GND 8
32 VCC 31 Q0 30 Q0 29 Q1 28 Q1 27 Q2 26 Q2 25 VCC
NB4N111K
NB4N111K
Exposed Pad (EP)
24 VCC 23 Q3 22 Q3 21 Q4 20 Q4 19 Q5 18 Q5 17 VCC
VCC 9 Q8 10 Q8 11 Q7 12 Q7 13 Q6 14 Q6 15
VCC 16
Figure 2. Pinout Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IREF
Output
Output current programming pin. Connect to GND. (See Figure 9).
2, 5
VTCLK,
−
Internal 50 W Termination Resistor connection Pins. In the differential configuration
VTCLK
when the input termination pins are connected to the common termination voltage,
and if no signal is applied then the device may be susceptible to self−oscillation.
3
CLK
LVPECL Input CLOCK Input (TRUE)
4
CLK
LVPECL Input CLOCK Input (INVERT)
8
GND
−
Supply Ground. GND pin must be externally connected to power supply to
guarantee proper operation.
9, 16, 17, 24, 25, 32
VCC
−
Positive Supply pins. VCC pins must be externally connected to a power supply to
guarantee proper operation.
6, 10, 12, 14, 18, 20, Q[09−0]
HCSL or Noninverted Clock Output. (For LVDS levels see Figure 15)
22, 26, 28, 30
LVDS Output
7, 11, 13, 15, 19, 21, Q[09−0]
HCSL or Inverted Clock Output. (For LVDS levels see Figure 15)
23, 27, 29, 31
LVDS Output
Exposed Pad
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing) must be attached to a sufficient heat−sinking conduit for proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
http://onsemi.com 2
NB4N111K
Table 2. ATTRIBUTES
Characteristic
Input Default State Resistors
ESD Protection
Human Body Model
Moisture Sensitivity (Note 2)
QFN32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value None >2 kV Level 1 UL 94 V−0 @ 0.125 in 622
Table 3. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC VI VINPP IOUT
Positive Power Supply Positive Input Differential Input Voltage Output Current
GND = 0 V
GND = 0 V
|CLK − CLK|
Continuous Surge
4.6
V
GND − 0.3 v VI v VCC V
VCC
V
50
mA
100
mA
TA
Operating Temperature Range
QFN32
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm
500 lfpm
QFN32 QFN32
−40 to +70
−65 to +150
31 27
°C
°C
°C/W °C/W
qJC
Thermal Resistance (Junction−to−Case)
2S2P (Note 4)
QFN32
12
°C/W
Tsol
Wave Solder
Pb−Free
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power). 4. JEDEC standard multila.