128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O
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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous D...
Description
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128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. 0.1 1.0 History Initial Draft Release Draft Date Jul. 2009 Aug. 2009 Remark Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Aug. 2009 1
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Synchronous DRAM Memory 128Mbit (8Mx16bit) H57V1262GFR Series DESCRIPTION
The Hynix H57V1262GFR series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. H57V1262GFR series is organized as 4banks of 2,097,152 x 16. H57V1262GFR is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or w...
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