72F521R9T6 ST72F521R9T6 Datasheet

72F521R9T6 Datasheet, PDF, Equivalent


Part Number

72F521R9T6

Description

ST72F521R9T6

Manufacture

STMicroelectronics

Total Page 30 Pages
Datasheet
Download 72F521R9T6 Datasheet


72F521R9T6
ST72521M/R/AR
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,
FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE
s Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 20 years at 55°C
s Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliary voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal or external RC oscillator,
clock security system and bypass for external
clock
– PLL for 2x frequency multiplication
– Four power saving modes: Halt, Active-Halt,
Wait and Slow
s Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin
– 15 external interrupt lines (on 4 vectors)
s Up to 64 I/O Ports
– 48 multifunctional bidirectional I/O lines
– 34 alternate function lines
– 16 high sink outputs
s 5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
– 8-bit PWM Auto-Reload timer with: 2 input
captures, 4 PWM outputs, output compare
Device Summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range (ROM)
Temp. Range (Flash)
Package
ST72(F)521(M/R/AR)9
60K
2048 (256)
up to -40°C to +125°C
TQFP80 14x14 (M), TQFP64
14x14 (R), TQFP64 10x10 (AR)
TQFP80
14 x 14
TQFP64
14 x 14
TQFP64
10 x 10
and time base interrupt, external clock with
event detector
s 4 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN com-
patible)
– I2C multimaster interface
– CAN interface (2.0B Passive)
s Analog peripheral
– 10-bit ADC with 16 input pins
s Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
s Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
ST72521(R/AR)7
48K
1536 (256)
3.8V to 5.5V
up to -40°C to +125°C
N/A
ST72(F)521(R/AR)6
32K
1024 (256)
up to -40°C to +125 °C
TQFP64 14x14 (R), TQFP64 10x10 (AR)
October 2002
Rev. 1.6
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72F521R9T6
Table of Contents
1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3.1 Read-out Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 ICP (IN-CIRCUIT PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 IAP (IN-APPLICATION PROGRAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.6.1 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1
5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.2 Asynchronous External RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.3 External Power-On RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.4 Internal Low Voltage Detector (LVD) RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.5 Internal Watchdog RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.1 Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2 Auxiliary Voltage Detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.3 Clock Security System (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6 EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.6.1 I/O Port Interrupt Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.7 EXTERNAL INTERRUPT CONTROL REGISTER (EICR) . . . . . . . . . . . . . . . . . . . . . . . 40
8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
199
8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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Features ST72521M/R/AR 8-BIT MCU WITH NESTED INTE RRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE s s s s s Memories – 32K to 60K dual volt age High Density Flash (HDFlash) or ROM with read-out protection capability. I n-Application Programming and In-Circui t Programming for HDFlash devices – 1 K to 2K RAM – HDFlash endurance: 100 cycles, data retention: 20 years at 55 C Clock, Reset And Supply Management Enhanced low voltage supervisor (LVD ) for main supply and auxiliary voltage detector (AVD) with interrupt capabili ty – Clock sources: crystal/ceramic r esonator oscillators, internal or exter nal RC oscillator, clock security syste m and bypass for external clock – PLL for 2x frequency multiplication – Fo ur power saving modes: Halt, Active-Hal t, Wait and Slow Interrupt Management Nested interrupt controller – 14 i nterrupt vectors plus TRAP and RESET Top Level Interrupt (TLI) pin – 15 external interrupt lines (on 4 vectors) Up to 64 I/O Ports – 48 multifunctional bidire.
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