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PHD2N60 Dataheets PDF



Part Number PHD2N60
Manufacturers NXP
Logo NXP
Description PowerMOS transistor
Datasheet PHD2N60 DatasheetPHD2N60 Datasheet (PDF)

Philips Semiconductors Product specification PowerMOS transistor PHD2N60 GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable off-state characteristics, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. QUICK REFE.

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Philips Semiconductors Product specification PowerMOS transistor PHD2N60 GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting featuring high avalanche energy capability, stable off-state characteristics, fast switching and high thermal cycling performance with low thermal resistance. Intended for use in Switched Mode Power Supplies (SMPS), motor control circuits and general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance MAX. 600 1.7 42 6 UNIT V A W Ω PINNING - SOT428 PIN 1 2 3 tab gate drain source DESCRIPTION PIN CONFIGURATION tab SYMBOL d g 2 drain 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER ID IDM PD ∆PD/∆Tmb VGS EAS IAS Tj, Tstg Continuous drain current Pulsed drain current Total dissipation Linear derating factor Gate-source voltage Single pulse avalanche energy Peak avalanche current Operating junction and storage temperature range CONDITIONS Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C Tmb > 25 ˚C VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V VDD ≤ 50 V; starting Tj = 25˚C; RGS = 50 Ω; VGS = 10 V MIN. - 55 MAX. 1.7 1.1 6.8 42 0.33 ± 30 45 1.7 150 UNIT A A A W W/K V mJ A ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 3 UNIT K/W K/W July 1997 www.DataSheet.in 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor PHD2N60 ELECTRICAL CHARACTERISTICS Tj = 25 ˚C unless otherwise specified SYMBOL V(BR)DSS ∆V(BR)DSS / ∆Tj RDS(ON) VGS(TO) gfs IDSS IGSS Qg(tot) Qgs Qgd td(on) tr td(off) tf Ld Ls Ciss Coss Crss PARAMETER Drain-source breakdown voltage Drain-source breakdown voltage temperature coefficient Drain-source on resistance Gate threshold voltage Forward transconductance Drain-source leakage current Gate-source leakage current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 0.25 mA VGS = 10 V; ID = 1 A VDS = VGS; ID = 0.25 mA VDS = 30 V; ID = 1 A VDS = 600 V; VGS = 0 V VDS = 480 V; VGS = 0 V; Tj = 125 ˚C VGS = ±30 V; VDS = 0 V ID = 2 A; VDD = 360 V; VGS = 10 V MIN. 600 2.0 0.5 TYP. 0.7 4.6 3.0 1.4 1 60 10 20 2 9 10 20 60 20 3.5 7.5 236 34 20 MAX. 6.0 4.0 100 500 200 25 3 15 UNIT V V/K Ω V S µA µA nA nC nC nC ns ns ns ns nH nH pF pF pF VDD = 300 V; ID = 2 A; RG = 24 Ω; RD = 150 Ω Measured from tab to centre of die Measured from source lead solder point to source bond pad VGS = 0 V; VDS = .


BMJ401013 PHD2N60 IDG-600


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