M58LR128KT

M58LR128KT M58LR128KB M58LR256KT M58LR256KB 128 or 256 Mbit (×16, multiple bank, multilevel interface, burst) 1.8 V supply Flash memories Preliminary Data Features ■ Supply voltage – VDD = 1.7 V to 2.0 V for program, erase and read – VDDQ = 1.7 V to 2.0 V for I/O buffers – VPP = 9 V for fast program Synchronous/asynchronous read – Synchronous burst read mode: 54 MHz, 66 MHz – Asynchronous page read mode – Random access: 70 ns, 85 ns Synchronous burst read suspend Programming time – 2.5 µs typical word program time using Buffer Enhanced Factory Program command Memory organization – Multiple bank memory array: 8 Mbit banks for the M58LR128KT/B 16 Mbit banks for the M58LR256KT/B – Parameter blocks (top or bottom location) Dual operations – Program/erase in one bank while read in others – No delay between read and write operations Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WP for block lock-down – Absolute write protection with VPP = VSS ■ ■ ■ ■ Not packaged separately ■ Security – 64 bit unique device number – 2112 bit user programmable OTP cells Common Flash interface (CFI) 100 000 program/erase cycles per block Electronic signature – Manufacturer code: 20h – Top device codes: M58LR128KT: 88C4h M58LR256KT: 880Dh – Bottom device codes M58LR128KB: 88C5h M58LR256KB: 880Eh ■ ■ ■ ■ ■ The M58LRxxxKT/B memories are only available as part of a multichip package. March 2008 Rev 3 1/111 www.numonyx.com 1 This...