Document
Analog Peripherals - 12-Bit ADC
• Up to 200 ksps • Up to 32 external single-ended inputs • VREF from on-chip VREF, external pin or VDD • Internal or external start of conversion source • Built-in temperature sensor
- Two Comparators
• Programmable hysteresis and response time • Configurable as interrupt or reset source • Low current
On-Chip Debug - On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping, inspect/modify memory and registers
- Superior performance to emulation systems using ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V - Typical operating current: 19 mA at 50 MHz;
- Typical stop mode current: 2 µA
High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F50x/F51x
Mixed Signal ISP Flash MCU Family
Memory - 4352 bytes internal data RAM (256 + 4096 XRAM) - 64 or 32 kB Flash; In-system programmable in
512-byte Sectors Digital Peripherals - 40, 33, or 25 Port I/O; All 5 V tolerant - CAN 2.0 Controller—no crystal required - LIN 2.1 Controller (Master and Slave capable); no
crystal required - Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports - Four general purpose 16-bit counter/timers - 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM functionality Clock Sources - Internal 24 MHz with ±0.5% accuracy for CAN and master LIN operation - External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes) - Can switch between clock sources on-the-fly; useful in power saving modes Packages - 48-Pin QFP/QFN (C8051F500/1/4/5) - 40-Pin QFN (C8051F508/9-F510/1) - 32-Pin QFP/QFN (C8051F502/3/6/7) Automotive Qualified - Temperature Range: –40 to +125 °C - Compliant to AEC-Q100
ANALOG PERIPHERALS
A 12-bit
M U
200 ksps
X ADC
TEMP SENSOR
Voltage VREG Comparators 0-1 VREF
DIGITAL I/O
UART 0 SMBus
SPI PCA Timers 0-3 CAN LIN
Ports 0-4 Crossbar
External Memory Interface
24 MHz PRECISION INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
64 kB ISP FLASH
FLEXIBLE INTERRUPTS
8051 CPU (50 MIPS)
DEBUG CIRCUITRY
4 kB XRAM POR WDT
Rev. 1.2 3/11
Copyright © 2011 by Silicon Laboratories C8051F500/1/2/3/4/5/6/7/8/9-F510/1
C8051F50x/F51x
2 Rev. 1.2
C8051F50x/F51x
Table of Contents
1. System Overview ..................................................................................................... 16 2. Ordering Information ............................................................................................... 20 3. Pin Definitions.......................................................................................................... 22 4. Package Specifications ........................................................................................... 30
4.1. QFP-48 Package Specifications........................................................................ 30 4.2. QFN-48 Package Specifications........................................................................ 32 4.3. QFN-40 Package Specifications........................................................................ 34 4.4. QFP-32 Package Specifications........................................................................ 36 4.5. QFN-32 Package Specifications........................................................................ 38 5. Electrical Characteristics ........................................................................................ 40 5.1. Absolute Maximum Specifications..................................................................... 40 5.2. Electrical Characteristics ................................................................................... 41 6. 12-Bit ADC (ADC0) ................................................................................................... 52 6.1. Modes of Operation ........................................................................................... 53
6.1.1. Starting a Conversion................................................................................ 53 6.1.2. Tracking Modes......................................................................................... 53 6.1.3. Timing ....................................................................................................... 54 6.1.4. Burst Mode................................................................................................ 55 6.2. Output Code Formatting .................................................................................... 57 6.2.1. Settling Time Requirements...................................................................... 57 6.3. Selectable Gain ................................................................................................. 58 6.3.1. Calculating the Gain Value.......................................................