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C8051F902 Dataheets PDF



Part Number C8051F902
Manufacturers Silicon Laboratories
Logo Silicon Laboratories
Description 12/10-Bit ADC MCU
Datasheet C8051F902 DatasheetC8051F902 Datasheet (PDF)

C8051F91x-C8051F90x Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU Ultra-Low Power - 160 uA/MHz in active mode (24.5 MHz clock) - 2 us wake-up time (two-cell mode) - 10 nA sleep mode with memory retention; - 50 nA sleep mode with brownout detector - 300 nA sleep mode with LFO (‘F912/02 only) - 600 nA sleep mode with external crystal Supply Voltage 0.9 to 3.6 V - One-cell mode supports 0.9 to 1.8 V operation (‘F911/01). ‘F912 and ‘F902 devices can operate from 0.9 to 3.6 V.

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C8051F91x-C8051F90x Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU Ultra-Low Power - 160 uA/MHz in active mode (24.5 MHz clock) - 2 us wake-up time (two-cell mode) - 10 nA sleep mode with memory retention; - 50 nA sleep mode with brownout detector - 300 nA sleep mode with LFO (‘F912/02 only) - 600 nA sleep mode with external crystal Supply Voltage 0.9 to 3.6 V - One-cell mode supports 0.9 to 1.8 V operation (‘F911/01). ‘F912 and ‘F902 devices can operate from 0.9 to 3.6 V continuously - Two-cell mode supports 1.8 to 3.6 V operation - Built-in dc-dc converter with 1.8 to 3.3 V output for use in one-cell mode - Built-in LDO regulator allows a high analog supply voltage and low digital core voltage - 2 built in supply monitors (brownout detectors) 12-Bit or 10-Bit Analog to Digital Converter - ±1 LSB INL (10-bit mode); ±1.5 LSB INL (12-bit mode, ‘F912/02 only) no missing codes - Programmable throughput up to 300 ksps (10-Bit Mode) or 75 ksps (12-bit mode, ‘F912/02 only) - Up to 15 external inputs - On-chip voltage reference - On-Chip PGA allows measuring voltages up to twice the reference voltage - 16-bit auto-averaging accumulator with burst mode provides increased ADC resolution - Data dependent windowed interrupt generator - Built-in temperature sensor High-Speed 8051 µC Core - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - Up to 25 MIPS throughput with 25 MHz clock - Expanded interrupt handler Memory - 768 bytes RAM - 16 kB (‘F912/1), or 8 kB (‘F902/1) Flash; In-system programmable Digital Peripherals - 16 port I/O; All 5 V tolerant with high sink  current and programmable drive strength Hardware SMBus™ (I2C™ Compatible), 2 x SPI™, and UART serial ports available concurrently Four general purpose 16-bit counter/timers Programmable 16-bit counter/timer array with six capture/compare modules and watchdog timer Clock Sources - Internal oscillators: 24.5 MHz, 2% accuracy supports UART operation; 20 MHz low power oscillator requires very little bias current. External oscillator: Crystal, RC, C, or CMOS clock SmaRTClock oscillator: 32 kHz crystal or internal low frequency oscillator (‘F912/02) or self-oscillate mode Can switch between clock sources on-the-fly; useful in implementing various power saving modes On-Chip Debug - On-chip debug circuitry facilitates full-speed, nonintrusive in-system debug (no emulator required) Two Comparators - Programmable hysteresis and response time - Configurable as wake-up or reset source - Up to 15 Capacitive Touch Sense Inputs 6-Bit Programmable Current Reference - Up to ±500 µA. Can be used as a bias or for generating a custom reference voltage PWM enhanced mode on ‘F912/02 devices - Provides 4 breakpoints, single stepping - Inspect/modify memory and registers - Complete development kit Packages - 24-pin QFN (4 x 4 mm) - 24-pin QSOP (easy to hand-solder) - Tested die available Temperature Range: –40 to +85 °C ANALOG PERIPHERALS A M U X DIGITAL I/O UART SMBus 2 x SPI PCA Timer 0 Timer 1 Timer 2 Timer 3 CRC Port 0 CROSSBAR 12/10-bit 75/300 ksps ADC + IREF Port 1 + – TEMP SENSOR VREF VREG – Port 2 VOLTAGE COMPARATORS 24.5 MHz PRECISION INTERNAL OSCILLATOR External Oscillator 20 MHz LOW POWER INTERNAL OSCILLATOR HARDW ARE SmaRTClock HIGH-SPEED CONTROLLER CORE 16/8 kB ISP FLASH FLEXIBLE INTERRUPTS 8051 CPU (25 MIPS) DEBUG CIRCUITRY 768 B SRAM POR W DT Rev. 1.0 9/10 Copyright © 2010 by Silicon Laboratories C8051F91x-C8051F90x www.DataSheet.in C8051F91x-C8051F90x 2 Rev. 1.0 www.DataSheet.in C8051F91x-C8051F90x Table of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 20 1.1.1. Fully 8051 Compatible.............................................................................. 20 1.1.2. Improved Throughput ............................................................................... 20 1.1.3. Additional Features .................................................................................. 20 1.2. Port Input/Output............................................................................................... 21 1.3. Serial Ports ....................................................................................................... 22 1.4. Programmable Counter Array ........................................................................... 22 1.5. SAR ADC with 16-bit Auto-Averaging Accumulator and  Autonomous Low Power Burst Mode ............................................................... 23 1.6. Programmable Current Reference (IREF0) ...................................................... 24 1.7. Comparators ..................................................................................................... 24 2. Ordering Information.........................................................


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