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CY7C0832BV Dataheets PDF



Part Number CY7C0832BV
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C08xxxV) FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
Datasheet CY7C0832BV DatasheetCY7C0832BV Datasheet (PDF)

CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features ■ ■ ■ ■ ■ ■ ■ Functional Description The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more .

  CY7C0832BV   CY7C0832BV


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CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features ■ ■ ■ ■ ■ ■ ■ Functional Description The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time. During a Read operation, data is registered for decreased cycle time. Each port contains a burst counter on the input address register. After externally loading the counter with the initial address, the counter increments the address internally (more details to follow). The internal Write pulse width is independent of the duration of the R/W input signal. The internal Write pulse is self-timed to allow the shortest possible cycle times. A HIGH on CE0 or LOW on CE1 for one clock cycle powers down the internal circuitry to reduce the static power consumption. One cycle with chip enables asserted is required to reactivate the outputs. Additional features include: readback of burst-counter internal address value on address lines, counter-mask registers to control the counter wrap around, counter interrupt (CNTINT) flags, readback of mask register value on address lines, retransmit functionality, interrupt flags for message passing, JTAG for boundary scan, and asynchronous Master Reset (MRST). The CY7C0833AV device in this family has limited features. See Address Counter and Mask Register Operations [16] on page 6 for details. True Dual-Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location Synchronous Pipelined Operation Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices Pipelined Output Mode Allows Fast Operation 0.18 micron CMOS for Optimum Speed and Power High Speed Clock to Data Access 3.3V Low Power ❐ Active as Low as 225 mA (typ) ❐ Standby as Low as 55 mA (typ) Mailbox Function for Message Passing Global Master Reset Separate Byte Enables on Both Ports Commercial and Industrial Temperature Ranges IEEE 1149.1 Compatible JTAG Boundary Scan 144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch) 120 TQFP (14 mm x 14 mm x 1.4 mm) Pb-Free Packages Available Counter Wrap Around Control ❐ Internal Mask Register Controls Counter Wrap Around ❐ Counter-Interrupt Flags to Indicate Wrap Around ❐ Memory Block Retransmit Operation Counter Readback on Address Lines Mask Register Readback on Address Lines Dual Chip Enables on Both Ports for Easy Depth Expansion ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 1. Product Selection Guide Density Part Number Maximum Speed (MHz) Maximum Access Time Clock to Data (ns) Typical Operating Current (mA) Package 512 Kbit (32K x 18) CY7C0837AV 167 4.0 225 144 FBGA 1 Mbit (64K x 18) CY7C0830AV 167 4.0 225 120 TQFP 144 FBGA 2 Mbit (128K x 18) CY7C0831AV 167 4.0 225 120 TQFP 144 FBGA 167 4.0 225 120 TQFP 144 FBGA 4 Mbit (256K x 18) CY7C0832AV CY7C0832BV [1] 133 4.4 225 120 TQFP 9 Mbit (512K x 18) CY7C0833AV 133 4.7 270 144 FBGA Note 1. CY7C0832AV and CY7C0832BV are functionally identical. Cypress Semiconductor Corporation Document #: 38-06059 Rev. *S • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 03, 2009 [+] Feedback www.DataSheet.in CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Logic Block Diagram [2] OEL R/WL B0L B1L OER R/WR B0R B1R CE0L CE1L CE0R CE1R DQ9L–DQ17L DQ0L–DQ8L 9 9 I/O Control I/O Control 9 9 DQ9R–DQ17R DQ0R–DQ8R Addr. Read Back True Dual-Ported RAM Array Addr. Read Back A0L–A18L CNT/MSKL ADSL CNTENL CNTRSTL CLKL CNTINTL 19 19 Mask Register Counter/ Address Register Mirror Reg TMS TDI TCK Mask Register Counter/ Address Register Mirror Reg A0R–A18R CNT/MSKR ADS CNTEN CNTRSTR CLKR CNTINTR Address Decode Address Decode Interrupt INTL MRST Logic Reset Logic JTAG TDO Interrupt Logic INTR Note 2. CY7C0837AV has 15 address bits, CY7C0830AV has 16 address bits, CY7C0831AV has 17 address bits, CY7C0832AV/CY7C0832BV has 18 address bits and CY7C0833AV has 19 address bits. Document #: 38-06059 Rev. *S Page 2 of 28 www.DataSheet.in [+] Feedback CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Configurations Figure 1. 144-Ball BGA (Top View) CY7C0837AV / CY7C0830AV / CY7C0831AV / CY7C0832AV / CY7C0833AV 1 2 3 4 5 6 7 8 9 10 11 12 A DQ17L DQ16L DQ14L DQ12L DQ10L DQ9L DQ9R DQ10R DQ12R DQ14R DQ16R DQ17R B A0L A1L DQ15L DQ13L DQ11L MRST NC DQ11R DQ13R DQ15R A1R A0R C A2L A3L CE1L [7] INTL CNTINTL [9] ADSL [8] ADSR [8] CNTINTR [9] INTR CE1R [7] A3R A2R D A4L A5L CE0L [8] NC VDD VDD VDD VDD NC CE0R [8] A5R A4R E A6L A7L B1L NC VDD VSS VSS VDD NC B1R A7R A6R F A8L A9L CL NC VSS.


CY7C0832AV CY7C0832BV CY7C0833AV


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