Document
CY7C1526KV18 CY7C1513KV18 CY7C1515KV18
72-Mbit QDR® II SRAM Four-Word Burst Architecture
72-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
■ Separate independent read and write data ports ❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz ■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches ■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems ■ Single multiplexed address input bus latches address inputs
for read and write ports ■ Separate port selects for depth expansion ■ Synchronous internally self-timed writes ■ QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH ■ Operates similar to QDR I device with one cycle read latency
when DOFF is asserted Low ■ Available in × 9, × 18, and × 36 configurations ■ Full data coherency, providing most current data ■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply ■ Available in 165-ball fine pitch ball grid array (FBGA) package
(13 × 15 × 1.4 mm) ■ Offered in both Pb-free and non Pb-free packages ■ Variable drive HSTL output buffers ■ JTAG 1149.1 compatible test access port ■ Phase-locked loop (PLL) for accurate data placement
Configurations
CY7C1526KV18 – 8M × 9 CY7C1513KV18 – 4M × 18 CY7C1515KV18 – 2M × 36
Functional Description
The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II read and write ports are independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 9-bit words (CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit words (CY7C1515KV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus ‘turnarounds’. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. For a complete list of related documentation, click here.
Selection Guide
Description Maximum operating frequency Maximum operating current
333 MHz 300 MHz 250 MHz 200 MHz Unit 333 300 250 200 MHz
× 9 600 560 490 Not Offered mA × 18 620 570 500 440 × 36 850 790 680 Not Offered
Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-00435 Rev. *W
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 17, 2017
CY7C1526KV18 CY7C1513KV18 CY7C1515KV18
Logic Block Diagram – CY7C1526KV18
D[8:0]
9
A(20:0) 21
K K DOFF
VREF WPS BWS[0]
Address Register
CLK Gen.
Control Logic
Write Add. Decode Read Add. Decode
Write Write Write Write Reg Reg Reg Reg
Address Register
21 A(20:0)
2M x 9 Array 2M x 9 Array 2M x 9 Array 2M x 9 Array
Read Data Reg. 36 18
18
Control Logic
Reg. Reg.
Reg. 9 9 9 9
RPS C C
9
CQ CQ Q[8:0]
Document Number: 001-00435 Rev. *W
Page 2 of 35
CY7C1526KV18 CY7C1513KV18 CY7C1515KV18
Logic Block Diagram – CY7C1513KV18
D[17:0]
18
A(19:0) 20
Address Register
K K DOFF
VREF WPS BWS[1:0]
CLK Gen.
Control Logic
Write Add. Decode Read Add. Decode
Write Write Write Write Reg Reg Reg Reg
Address Register
20 A(19:0)
1M x 18 Array 1M x 18 Array 1M x 18 Array 1M x 18 Array
Read Data Reg. 72 36
36
Control Logic
RPS
C C
Reg. Reg.
Reg. 18 18 18 18
18
CQ CQ Q[17:0]
Document Number: 001-00435 Rev. *W
Page 3 of 35
CY7C1526KV18 CY7C1513KV18 CY7C1515KV18
Logic Block Diagram – CY7C1515KV18
D[35:0]
36
A(18:0) 19
Address Register
K K DOFF
VREF WPS BWS[3:0]
CLK Gen.
Control Logic
Write Add. Decode Read Add. Decode
Write Write Write Write Reg Reg Reg Reg
Address Register
19 A(18:0)
512K x 36.