GSC3E

Datasheet SiRFstarIII Architecture GSC3e/LPx and GSC3f/LPx PRODUCT DESCRIPTION High Performance, Lowest Power, GPS Single Chip GSW3—Modular Software Support X X The GSC3e/LPx and GSC3f/LPx are the pin-for-pin compatible, lowest power versions of the advanced GSC3e(f)/LP receiver in a single package. The baseband has been ported to 65 nm technology, enabling an additional power reduction of up to 30 percent. In the GSC3e/LPx, the baseband and RF are integrated into the 7 mm x 10 mm x 1.4 mm package. In the GSC3f/LPx, flash memory is included in the package making for an extremely compact design. The GSC3e(f)/LPx includes a powerful GPS DSP integrated with an ARM7TDMI microprocessor and 1 Mb of SRAM. The GSC3e(f)/LPx architecture uses an FFT and Matched Filter that delivers performance equivalent to more than 200,000 correlators. This represents a quantum leap forward in GPS performance. API compatible with GSW2 RTOS friendly PRODUCT HIGHLIGHTS GSC3f/LPx—Digital, RF, and Flash Single Chip X X X X X Digital, RF, and 4 Mb Flash in a single package Small 7 mm x 10 mm x 1.4 mm, BGA package ARM7TDMI CPU and SRAM to enable user tasks Accepts six reference frequencies between 13 MHz and 26 MHz Extensive GPS peripherals: 2 UARTs, battery-backed SRAM, and 14 GPIOs ARCHITECTURE HIGHLIGHTS Next Generation, Lowest Power, GPS Performance X X X X X X X Lowest Power X X X Under 60 mW at full power 46 mW tracking power Push-to-Fix™ reduces power as much as 98% 200,000+ effective corr...