AS9C25256M2036L

September 2004 Preliminary Information ® AS9C25256M2036L AS9C25128M2036L www.DataSheet4U.com 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface Features True Dual-Port memory cells that allow simultaneous access of the same memory location Organisation: 262,144/131,072 x 36[1] Fully Synchronous, independent operation on both ports Selectable Pipeline or Flow-Through output mode Fast clock speeds in Pipeline output mode: 250 MHz operation (18Gbps bandwidth) Fast clock to data access: 2.8ns for Pipeline output mode Asynchronous output enable control Fast OE access times: 2.8ns Double Cycle Deselect (DCD) for Pipeline Output Mode 18/17[1]-bit counter with Increment, Hold and Repeat features on each port Dual Chip enables on both ports for easy depth expansion Note: 1. AS9C25256M2036L/AS9C25128M2036L Interrupt and Collision Detection Features 2.5 V power supply for the core LVTTL compatible, selectable 3.3V or 2.5V power supply for I/Os, addresses, clock and control signals on each port Snooze modes for each port for standby operation 15mA typical standby current in power down mode Available in 256-pin Ball Grid Array (BGA), 208-pin Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball Grid Array (fpBGA) Supports JTAG features compliant with IEEE 1149.1 Selection guide Feature Minimum cycle time Maximum Pipeline clock frequency Maximum Pipeline clock access time Maximum flow-through clock frequency Maximum flow-t...