9Mb Synchronous Burst SRAMs
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
100-Pin TQFP Commercial Temp Industrial Temp Features
• Flow Through mode operation...
Description
GS880F18/32/36AT-5.5/6/6.5/7/7.5/8.5
100-Pin TQFP Commercial Temp Industrial Temp Features
Flow Through mode operation; Pin 14 = No Connect 2.5 V or 3.3 V +10%/–10% core power supply 2.5 V or 3.3 V I/O supply LBO pin for Linear or Interleaved Burst mode Internal input resistors on mode pins allow floating mode pins Default to Interleaved Pipeline mode Byte Write (BW) and/or Global Write (GW) operation Internal self-timed write cycle Automatic power-down for portable applications JEDEC-standard 100-lead TQFP package
512K x 18, 256K x 32, 256K x 36 9Mb Synchronous Burst SRAMs
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5.5 ns–8.5 ns 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Designing for Compatibility The JEDEC standard for Burst RAMS calls for a FT mode pin option on Pin 14. Board sites for flow through Burst RAMS should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s pipeline/flow through-configurable Burst RAMs or any vendor’s flow through or configurable Burst SRAM. Boards designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, like this RAM, to achieve flow through functionality. Byte Write and Global Write Byte write...
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