Document
September 2006 rev 0.1 Low Power Peak EMI Reducing clock synthesizer
PCS3P7101A
www.DataSheet4U.com
Features
• • • • • • • • Generates a 4x low EMI clock at the output Input frequency: 25 MHz Integrated loop filter components. Frequency deviation: ±0.25% (Typ) center spread Operates with a 3.3V Supply. Low power CMOS design. Available in 8-pin SOIC package. Pin compatible with ICS 341-22
Product Description
The PCS3P7101A is a low cost, single-output, clock synthesizer. The PCS3P7101A generates a 4x output clock from a 25 MHz standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving valuable board space and cost. The device employs Spread Spectrum technique to reduce system electro-magnetic interference (EMI). The device also has a power-down feature that tri-state the clock output and turns off the PLL when the PD pin is taken low.
Block Diagram
VDD PD
Modulation XIN/CLKIN XOUT Crystal Oscillator Frequency Divider Feedback Divider Phase Detector Loop Filter
PLL
VCO
Output Divider ModOUT
VSS
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
September 2006 rev 0.1
Pin Configuration
CLKIN/XIN 1 VDD 2
8 XOUT
PCS3P7101A
www.DataSheet4U.com
7
PD
PCS3P7101A
VSS 3 NC 4
6 NC 5 ModOUT
Pin Description Pin # Pin Name
1 2 3 4 5 6 7 8 CLKIN/XIN VDD VSS NC ModOUT NC PD XOUT
Type
I P P O I O
Description
Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or to an external reference clock. Power supply for the entire chip. Ground connection No Connection Spread spectrum low EMI 4x clock output. No Connection Powers down entire chip. Tri-states CLK outputs when low. Has an Internal pull-up resistor. Crystal connection. If using an external reference, this pin must be left unconnected
Absolute Maximum Ratings Symbol
VDD, VIN TSTG TA Ts TJ TDV Storage temperature Operating temperature
Parameter
Rating
-0.5 to +4.6 -65 to +125 0 to +70 260 150 2
Unit
V °C °C °C °C KV
Voltage on any pin with respect to Ground
Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD 22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Recommended Operating Conditions1 Parameter
Supply voltage, VDD Low-level input voltage, VIL High-level input voltage, VIH High-level output current, IOH Low-level output current, IOL VDD = 3.15V to3.45V VDD = 3.15V to3.45V VDD = 3.15V to3.45V VDD = 3.15V to3.45V
Min
3.15 2 0
Typ
3.3 -
Max
3.45 0.8 12 12 70
Unit
V V V mA mA °C
Operating free-air temperature, TA
Note:1 Unused inputs must be held high or low to prevent them from floating.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
2 of 7
September 2006 rev 0.1
DC Electrical Characteristics Symbol Parameter
VIL VIH IIL IIH VOL VOH IDD ICC VDD ZOUT CIN RPD RPUP Input low voltage Input high voltage Input low current Input high current Output low voltage (VDD = 3.3 V, IOL = 12 mA) Output high voltage (VDD = 3.3 V, IOH = 12 mA) Static supply current* Dynamic supply current (3.3V, 25MHz and no load) Operating voltage Output impedance
PCS3P7101A
Min
VSS - 0.3 2.0 2.4 3.15 -
Typ
50 TBD 3.3 20
Max Unit www.DataSheet4U.com
0.8 VDD + 0.5 -35 35 0.4 _ 3.45 V Ω V V µA µA V V uA
Input Capacitance Internal pull-up resistor PD CLK output
4 250 525
pF
KΩ kΩ
* XIN/CLKIN pin and PD pin are pulled low
AC Electrical Characteristics for 3.3V Supply Symbol
CLKIN/XIN ModOUT Input frequency Output frequency Output rise time (measured from 0.8 to 2.0V) Output fall time (measured at 2.0V to 0.8V)
Parameter
Min
40 -
Typ
25 100 1 1 4 4 0 TBD TBD 50 TBD
Max
10 7 60 -
Unit
MHz MHz nS nS mS mS ppm pS pS % pS
tLH* tHL*
tPU tON
Power-up time( PLL lock time from power-up)
Power-up time (first locked cycle after power-up)**
Synthesis Error(Output Frequency) tJC tJP tD tja
Jitter (cycle to cycle)
Period Jitter
Output duty cycle
Maximum Absolute Jitter
*tLH and tHL are measured into a capacitive load of 15pF ** VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Low Power Peak EMI Reducing clock synthesizer
Notice: The information in this document is subject to change without notice.
3 of 7
September 2006 rev 0.1
Typical Crystal Oscillator Circuit
PCS3P7101A
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R1 = 510Ω
C1 = 27 pF
C2 = 27 pF
Typical Crystal Specifications Fundamental AT cut parallel resonant crystal
Nominal frequency Frequency tolerance Operating temperature range Storage temperature Load capacitance Shunt capacitance ESR 25MHz ± 50 ppm or better at 25°C -25°C to +85°C -40°C to +.