UMC5N

UMC5N DUAL COMPLEMENTARY PRE-BIASED TRANSISTORS Features Epitaxial Planar Die Construction Surface Mount Package Suited for Automated Assembly Simplifies Circuit Design and Reduces Board Space Lead Free/RoHS Compliant (Note 1) "Green" Device (Note 2) SOT-353 3 2 1 (3) (2) R1 R2 Q2 R2 Q1 R1 (5) (1) Q1 R1 = 47kΩ R2 = 47kΩ Q2 R1 = 4.7kΩ R2 = 10kΩ NEW PRODUCT Mechanical Data Case: SOT-353 Case Material: Molded Plastic. UL Flammability Classification Rating 94V-0 Moisture Sensitivity: Level 1 per J-STD-020C Terminal Connections: See Diagram Terminals: Finish – Matte Tin Annealed Over Alloy 42 Leadframe. Solderable per MIL-STD-202, Method 208 Marking Information: See Page 4 Ordering Information: See Page 4 Weight: 0.006 grams (approximate) 4 5 (4) TOP VIEW Schematic and Pin Configuration Maximum Ratings, Total Device @TA = 25°C unless otherwise specified Symbol PD RθJA Tj, TSTG Value 150 833 -55 to +150 Unit mW °C/W °C Characteristic Power Dissipation (Note 3) Thermal Resistance, Junction to Ambient Air (Note 3) Operating and Storage Temperature Range Maximum Ratings, Pre-Biased NPN Transistor, Q1 Characteristic Supply Voltage Input Voltage Output Current Collector Current @TA = 25°C unless otherwise specified Value 50 -10 to +40 30 100 Unit V V mA mA Symbol VCC VIN IO IC(MAX) Maximum Ratings, Pre-Biased PNP Transistor, Q2 Characteristic Supply Voltage Input Voltage Output Current Collector Current Notes: @TA = 25°C unless otherwise specifie...