HY5S5B2BLFP-6E

256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series 11 Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 : 85mA --> 90mA 133MHz IDD1 : 70mA --> 75mA 105MHz IDD1 : 50mA --> 60mA 2. Remove CL2 operation (Page 13 to 14) 1. Release History Draft Date Nov. 2005 Remark Preliminary 0.2 Mar. 2006 Preliminary 1.0 Apr. 2006 Final Rev 1.0 / Apr. 2006 2 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2BLF(P) Series 11 DESCRIPTION The Hynix HY5S5B2BLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (C...