HY5S5B2CLFP-HE

256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.5 / Aug. 2008 1 11 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2CLF(P) Series Document Title 4Bank x 2M x 32bits Synchronous DRAM Revision History Revision No. 0.1 0.2 1.0 1.1 1.2 Initial Draft Initial Draft Release Correct IDD5 value: 85mA max -> 110mA max Insert (Page11) DPD specification [IDD7: 10uA min] - Updated Auto Refresh cycle during Power-up and Initialization Sequence (8 cycles to 2 cycles) - Editorial changes in some descriptions - Corrected the description of BURST TERMINATE - Corrected the CJE state on every command - Typo Corrected. History Draft Date Nov. 2006 Apr. 2007 June. 2007 June. 2007 July. 2007 Remark Preliminary Preliminary 1.3 May 2008 1.4 1.5 Jun. 2008 Aug. 2008 Rev 1.5 / Aug. 2008 2 11 256Mbit (8Mx32bit) Mobile SDR Memory HY5S5B2CLF(P) Series DESCRIPTION The Hynix HY5S5B2CLF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, hand-held PCs. The Hynix 256M Mobile SDRAM is 268,435,456-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications...