HY5S7B6LFP-S

512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 Initial Draft Package size (10 x 13 [mm2]) Defined DC Chatacteristics (Page 10 ~ 11) Modified Address # in Ball Description and Figures Final Version History Draft Date Oct. 2004 May. 2005 Aug. 2006 Aug. 2006 Jan. 2007 Remark Preliminary Preliminary Preliminary Preliminary www.DataSheet4U.com This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jan. 2007 1 512Mbit (32Mx16bit) Mobile SDR Memory HY5S7B6LF(P) Series 11 DESCRIPTION The Hynix HY5S7B6LF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous DRAM(Mobile SDR), ideally suited for the main memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 8,388,608x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on...