SCG102A

SCG102A Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com Applications SONET / SDH / ATM DWDM / FDM DSL-PON Interconnects FEC (Forward Error Correction) Features 3.3V High Precision PLL Accepts 1 of 4 Selectable, Pre-determined Input Frequencies 77.76 MHz to 170 MHz Output Frequencies Available. Jitter Generation OC-192 Compliant www.DataSheet4U.com 1.0” x 0.80” x 0.285”, Surface Mount Bulletin Page Revision Date Issued By SG076 1 of 8 00 11 APR 07 ENG General Description The SCG102A provides high precision phase lock loop frequency translation for the telecommunication applications. The SCG102A product generates LVPECL outputs from an intrinsically low jitter, voltage controlled crystal oscillator. SCG102A is well suited for use in line cards, service termination cards and similar functions to provide reliable reference, phase locked, synchronization for TDM, PDH, SONET and SDH network equipment . The SCG102A provides a jitter filtered, wander following output signal sychronized to a superior Stratum or peer input reference signal. The SCG102A includes a lock detect alarm output. The PLL control voltage is brought out through a 470 kΩ restistor and can be used to determine when the pull range limits are reached.The LVPECL outputs may be put into the tri-state high impedance condition for external testing purposes by asserting a high signal to the Enable/Disable pin...