SCG4521

SCG4521 Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features Dual 19.44 MHz Input References Primary 155.52 MHz LVPECL Outputs with Disable Function Secondary 51.84 MHz CMOS Output Phase Locked Output Frequency Control Intrinsically Low Jitter Crystal Oscillator LOR & LOL Alarm Force Free Run Function www.DataSheet4U.com Automatic Free Run operation on loss of both References A & B Input Duty Cycle Tolerant 3.3V dc Power Supply Bulletin Page Revision Date Issued By SG036 1 of 16 A02 25 Oct 01 MBatts Small Size: 1 Square Inch General Description The SCG4521 is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4521 can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4521 provides two types of output logic. The primary output is a differential LVPECL output at 155.52 MHz. The secondary output is a CMOS output at 51.84 MHz that is derived from the LVPECL output. Both outputs are phase aligned to the selected input reference. The SCG4521 includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the ala...