CY14B101J

PRELIMINARY 1 Mbit (128 K × 8) Serial (I C) nvSRAM Features ■ ■ CY14C101J CY14B101J, CY14E101J 2 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 128 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor (except for CY14X101J1) High reliability ❐ ❐ ❐ Industry standard configurations ❐ Operating voltages: CY14C101J: VCC = 2.4 V to 2.6 V CY14B101J: VCC = 2.7 V to 3.6 V CY14E101J: VCC = 4.5 V to 5.5 V ❐ Industrial temperature ❐ 8- and 16-pin small outline integrated circuit (SOIC) package ❐ Restriction of hazardous substances (RoHS) compliant Overview The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM[1] with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X101J1). On power-up, data is restored to the SRAM from the nonvolatile memory...