CY7C1481V25

CY7C1481V25 CY7C1483V25 CY7C1487V25 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM Features Supports 133 MHz bus operations 2M x 36/4M x 18/1M x 72 common IO 2.5V core power supply (VDD) 2.5V or 1.8V IO supply (VDDQ) Fast clock-to-output time Functional Description[1] The CY7C1481V25/CY7C1483V25/CY7C1487V25 is a 2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1481V25/CY7C1483V25/CY7C1487V25 enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) in...