Document
CMS3232LAx-75Ex
32M(1Mx32) Low Power SDRAM
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Revision 0.2 August, 2006
Rev0.2, Aug. 2006
CMS3232LAx-75Ex
Document Title
32M(1Mx32) Low Power SDRAM
Revision History Revision No.
0.0 0.1 0.2 Initial Draft Add H(Pb-Free & Halogen Free) descriptions Changed min Vcc to 1.70V
History
Draft date
Mar. 3rd, 2005 Nov. 1st, 2005 Aug. 7th, 2006
Remark
Preliminary Final Final
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Rev0.2, Aug. 2006
CMS3232LAx-75Ex
Features
- Functionality - Standard SDRAM Functionality - Programmable burst lengths : 1, 2, 4, 8, or full page - JEDEC Compatibility - Low Power Features - Low voltage power supply : 1.8V - Auto TCSR(Temperature Compensated Self Refresh) - Partial Array Self Refresh power-saving mode - Deep Power Down Mode - Driver Strength Control - Operating Temperature Ranges: - Special (-10℃ to +60℃) - Commercial (0℃ to +70℃) - Extended (-25℃ to +85℃) - Industrial (-40℃ to +85℃) - LVCMOS Compatible IO Interface - 90ball FBGA with 0.8mm ball pitch - CMS3232LAF : Normal - CMS3232LAG : Pb-Free - CMS3232LAH : Pb-Free & Halogen Free
Functional Description
The CMS3232LAx-xxxx family is high-performance CMOS Dynamic RAMs (DRAM) organized as 1M x 32. These devices feature advanced circuit design to provide ultra-low active current and extremely low standby current.This is ideal for providing More Battery Life in portable applications such as wireless handsets. The device is compatible with the JEDEC standard LP-SDRAM specifications.
Logic Block Diagram
CKE CLK /CS /WE /CAS /RAS
Control Logic
Refresh Counter Row Add Mux
Bank 1 Bank 0 Bank 0 Bank Row0 Row Addr Addr Latch/ Latch/ Decoder Decoder Memory Array 2Kx8K DQM0DQM3 Data Output Reg
Mode Reg Enhanced Mode Reg
Sense Amp
Bank Control Logic A0-A10 BS Addr Reg Column Column Decoder Decoder Column Address Latch
Write Drivers DQM Mask READ DATA LATCH
DQ0 DQ31 Data Input Reg
Selection Guide www.DataSheet4U.com
Device VDD CMS3232LAx-75Ex
Voltage Frequency VDDQ 133MHz 1.70-VDD
Access Time(tAC) CL=2 CL=3 7ns 8ns
tRCD 20ns 20ns
tRP 20ns 20ns
1.70-1.95V
100MHz
Rev0.2, Aug. 2006
CMS3232LAx-75Ex
Pin Configuration
90 ball 0.8mm pitch FBGA(8mm x 13mm)
Top View
1
2
3
4
5
6
7
8
9
A
DQ26
DQ24
VSS
VDD
DQ23
DQ21
B
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
C
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
D
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
H
A7
A8
NC
NC
NC
NC
J
CLK
CKE
A9
BS
/CS
/RAS
K
DQM1
NC
NC
/CAS
/WE
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
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P
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ13
DQ15
VSS
VDD
DQ0
DQ2
Rev0.2, Aug. 2006
CMS3232LAx-75Ex
Pin Description
Symbol CLK Type Input Description Clock : CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), ACTIVE POWER-DOWN(row active in any bank) or CLOCK SUSPEND operation(burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Command Inputs : /CAS, /RAS, and /WE (along with /CS) define the command being entered. Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. DQM0 corresponds to DQ0 – DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, AND DQM3 corresponds to DQ24–DQ31. Bank Address Input(s): BS define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op-code during a LOAD MODE REGISTER command. Address Inputs: A0–A10 are sampled during the ACTIVE command (row-address A0–A10) and READ/WRITE command (column-address A0–A7; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BS (A10 LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output : Data bus No Connect D.