STP40NS15

N-CHANNEL 150V - 0.042Ω - 40A TO-220 MESH OVERLAY™ MOSFET PRELIMINARY DATA TYPE STP40NS15 s s s s STP40NS15 VDSS 150 V RDS(on) <0.052Ω ID 40A TYPICAL RDS(on) = 0.042Ω EXTREMELY HIGH dv/dt CAPABILITY VERY LOW INTRINSIC CAPACITANCES GATE CHARGE MINIMIZED 3 1 2 DESCRIPTION This powermos MOSFET is designed using the company’s consolidated strip layout-based MESH OVERLAY™ process. This technology matches and improves the performances compared with standard parts from various sources. TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS s HIGH CURRENT SWITCHING s UNINTERRUPTIBLE POWER SUPPLY (UPS) s PRIMARYSWITCH IN ISOLATED DC-DC CONVERTERS ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM (q ) PTOT dv/dt Tstg Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuos) at TC = 25°C Drain Current (continuos) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Storage Temperature Value 150 150 ±20 40 25 160 140 0.933 9 –65 to 175 175 Unit V V V A A A W W/°C V/ns °C °C Tj Max. Operating Junction Temperature www.DataSheet4U.com ()Pulse width limited by safe operating area October 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/6 STP40NS15 THERMAL DATA Rthj-case Rthj-amb Rthc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-amb...