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CY7C11651KV18 Dataheets PDF



Part Number CY7C11651KV18
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 18-Mbit QDR II SRAM 4-Word Burst Architecture
Datasheet CY7C11651KV18 DatasheetCY7C11651KV18 Datasheet (PDF)

18-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 ® Features ■ Functional Description The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port.

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18-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 18-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 ® Features ■ Functional Description The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Accesses to the QDR II+ read and write ports are completely independent of one another. To maximize data throughput, both read and write ports are equipped with DDR interfaces. Each address location is associated with four 8-bit words (CY7C11611KV18), 9-bit words (CY7C11761KV18), 18-bit words (CY7C11631KV18), or 36-bit words (CY7C11651KV18) that burst sequentially into or out of the device. Because data is transferred into and out of the device on every rising edge of both input clocks (K and K), memory bandwidth is maximized while simplifying system design by eliminating bus “turn arounds”. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65 nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65 nm Technology Interim QDRII+/DDRII+ SRAM Device Family Description. Table 1. Selection Guide Description Maximum Operating Frequency Maximum Operating Current 550 500 450 400 MHz MHz MHz MHz Unit 550 x8 900 x9 900 x18 920 500 830 830 850 450 760 760 780 400 690 690 710 MHz mA Separate independent read and write data ports ❐ Supports concurrent transactions 550 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz Available in 2.5 clock cycle latency Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Echo clocks (CQ and CQ) simplify data capture in high speed systems Data valid pin (QVLD) to indicate valid data on the output Single multiplexed address input bus latches address inputs for read and write ports Separate port selects for depth expansion Synchronous internally self timed writes QDR® II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW Available in x8, x9, x18, and x36 configurations Full data coherency, providing most current data Core VDD = 1.8V± 0.1V; I/O VDDQ = 1.4V to VDD [1] ❐ Supports both 1.5V and 1.8V I/O supply HSTL inputs and variable drive HSTL output buffers Available in 165-ball FBGA package (13 x 15 x 1.4 mm) Offered in both Pb-free and non Pb-free packages JTAG 1149.1 compatible test access port Phase Locked Loop (PLL) for accurate data placement ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Configurations With Read cycle latency of 2.5 cycles: CY7C11611KV18 – 2M x 8 www.DataSheet4U.com CY7C11761KV18 – 2M x 9 CY7C11631KV18 – 1M x 18 CY7C11651KV18 – 512K x 36 x36 1310 1210 1100 1000 Cypress Semiconductor Corporation Document Number: 001-53197 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 31, 2011 [+] Feedback CY7C11611KV18, CY7C11761KV18 CY7C11631KV18, CY7C11651KV18 Logic Block Diagram (CY7C11611KV18) D[7:0] 8 Read Add. Decode Write Add. Decode A(18:0) 19 Write Reg Address Register Write Reg Write Reg Write Reg Address Register 19 A(18:0) 512K x 8 Array 512K x 8 Array 512K x 8 Array 512K x 8 Array K K CLK Gen. Control Logic RPS DOFF Read Data Reg. CQ 32 VREF WPS NWS[1:0] 16 Control Logic 16 Reg. Reg. Reg. 8 8 8 8 CQ 8 Q[7:0] QVLD Logic Block Diagram (CY7C11761KV18) D[8:0] 9 Read Add. Decode Write Add. Decode A(18:0) 19 Write Reg Address Register Write Reg Write Reg Write Reg Address Register 19 A(18:0) 512K x 9 Array 512K x 9 Array 512K x 9 Array 512K x 9 Array K K CLK Gen. Control Logic RPS DOFF Read Data Reg. CQ 36 VREF WPS BWS[0] www.DataSheet4U.com 18 Control Logic 18 Reg. Reg. Reg. 9 9 9 9 CQ 9 Q[8:0] QVLD Note 1. Th.


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