CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18
18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
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Configurations
With Read Cycle Latency of 2.5 cycles: CY7C1161KV18 – 2 M x 8 CY7C1176KV18 – 2 M x 9 CY7C1163KV18 – 1 M x 18 CY7C1165KV18 – 512 K x 36
Separate independent read and write data ports ❐ Supports concurre...
