CY7C1424AV18

CY7C1422AV18 CY7C1429AV18 CY7C1423AV18 CY7C1424AV18 36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300-MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–VDD) Available in 165-ball FBGA package (15 x 17 x 1.4 mm) Offered in both lead-free and non lead-free packages JTAG 1149.1 compatible test access port Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1422V18, CY7C1429AV18, CY7C1423V18, CY7C1424V18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports to access the memory array. The Read port has dedicated Data outputs and the Write port has dedicated Data inputs to completely eliminate the need to “turn around’ the data bus required with common I/O devices. Access to each port is accomplished using a common address bus. Addresses for Read and Write are latc...