CY7C1320BV18

CY7C1316BV18 CY7C1916BV18 CY7C1318BV18 CY7C1320BV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Features 18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36) 300-MHz clock for high bandwidth 2-Word burst for reducing address bus frequency Double Data Rate (DDR) interfaces (data transferred at 600 MHz) @ 300 MHz Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches Echo clocks (CQ and CQ) simplify data capture in high-speed systems Synchronous internally self-timed writes 1.8V core power supply with HSTL inputs and outputs Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–VDD) Available in 165-ball FBGA package (13 x 15 x 1.4 mm) Offered in both lead-free and non lead-free packages JTAG 1149.1-compatible test access port Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each ...