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CY62147CV25 Dataheets PDF



Part Number CY62147CV25
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 256K x 16 Static RAM
Datasheet CY62147CV25 DatasheetCY62147CV25 Datasheet (PDF)

47V CY62147CV25/30/33 MoBL™ 256K x 16 Static RAM Features • High Speed — 55 ns and 70 ns availability • Voltage range: — CY62147CV25: 2.2V–2.7V — CY62147CV30: 2.7V–3.3V — CY62147CV33: 3.0V–3.6V • Pin Compatible with CY62147V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • — Typical active current: 5.5 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power cantly .

  CY62147CV25   CY62147CV25



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47V CY62147CV25/30/33 MoBL™ 256K x 16 Static RAM Features • High Speed — 55 ns and 70 ns availability • Voltage range: — CY62147CV25: 2.2V–2.7V — CY62147CV30: 2.7V–3.3V — CY62147CV33: 3.0V–3.6V • Pin Compatible with CY62147V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz • • • • — Typical active current: 5.5 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE and OE features Automatic power-down when deselected CMOS for optimum speed/power cantly reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62147CV25/30/33 are available in a 48-ball FBGA package. Functional Description The CY62147CV25/30/33 are high-performance CMOS static RAMs organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that signifi- Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array 2048 x 2048 SENSE AMPS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER BHE WE CE OE BLE A11 A12 A13 A14 A15 A16 CE Pow er Down Circuit BHE BLE Cypress Semiconductor Corporation Document #: 38-05202 Rev. *A • 3901 North First Street A17 www.DataSheet4U.com • San Jose • CA 95134 • 408-943-2600 Revised April 24, 2002 CY62147CV25/30/33 MoBL™ Pin Configuration[1, 2] 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 FBGA (Top View) 4 3 5 A0 A3 A5 A17 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vcc Vss I/O6 I/O7 NC A B C D E F G H I/O12 DNU I/O13 NC A8 A14 A12 A9 M.


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