CY62147DV18

CY62147DV18 MoBL2™ 4-Mb (256K x 16) Static RAM Features Very high speed: 55 ns and 70 ns Wide voltage range: 1.65V – 2.25V Pin-compatible with CY62147CV18 Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 6 mA @ f = fmax Ultra low standby power Easy memory expansion with CE, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered 48-ball BGA mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Writing to the device is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by asserting Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enab...