NOR FLASH MEMORY
8-, 16-Word Linear Burst Read
As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap, in which a fixed number of words are read from consecutive
addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized
according to the number of words read in a single burst sequence for a given mode. (Refer to Table 9)
[Table 9] Burst Address Groups (Wrap mode)
Group Address Ranges
0-7h, 8-Fh, 10-17h, ....
0-Fh, 10-1Fh, 20-2Fh, ....
As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst
sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the
selected group. In a similar manner, 16-word wrap mode begins its burst sequence on the starting address written to the device, and then wrap back to
the first address in the selected address group.
9.2 Programmable Wait State
The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from low to high for
burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen.
The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready
to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode
Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data.(RDY can be low active by
Extended configuration register A11 setting : RDY low indicates data valid) Using the autoselect command sequence, the handshaking feature will be ver-
ified in the device.
9.4 Set Burst Mode Configuration Register
The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode
configuration register must be set before the device enters burst mode. The burst mode configuration register is loaded with a three-cycle command
sequences. On the third cycle, the data should be C0h, address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be
latched. The device returns to default setting after power up or hardware reset.
9.4.1. Programmable Wait State Configuration
This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available. This value
is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Configuration Register Table 10.) The Programma-
ble wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will revert
the wait state to the default setting, that is 14 initial cycles.
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