PA7140

Commercial/ Industrial PA7140 PEELTM Array Features s Programmable Electrically Erasable Logic Array s Versatile Logic Array Architecture - 24 I/Os, 14 inputs, 60 registers/latches - Up to 72 logic cell output functions - PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried High-Speed Commercial and Industrial Versions - As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX) - Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications - Integration of multiple PLDs and random logic - Buried counters, complex state-machines - Comparators, decoders, other wide-gate functions CMOS Electrically Erasable Technology , - Reprogrammable in 40-pin DIP 44-pin PLCC, and TQFP packages Flexible Logic Cell - Up to 3 output functions per logic cell - D,T and JK registers with special features - Independent or global clocks, resets, presets, clock polarity and output enables - Sum-of-products logic for output enables Development and Programmer Support - ICT PLACE Development Software -Fitters for ABEL, CUPL and other software -Programming support for by ICT PDS-3 and popular third-party programmers s s s General Description The PA7140 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibilit...